An 800MHz -122dBc/Hz-at-200kHz clock multiplier based on a combination of PLL aid recirculating DLL

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages

  Gierkink, Sander ^a  

^a Conexant Systems ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK MULTIPLIERS; INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE; PHASE-NOISE;

FREQUENCY MULTIPLYING CIRCUITS; PHASE LOCKED LOOPS;

CLOCKS;

EID: 48849100170     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523253     Document Type: Conference Paper

References (3)

1. R. Farjad-Rad, W. Dally, Ng Hiok-Tiaq et. al. "A Low-Power Multiplying DLL for Low-Jitter Multigigahertz Clock Generation in Highly Integrated Digital Chips," IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1804-1812, Dec. 2002.
2. P.C. Maulik and D.A. Mercer, "A DLL-Based Programmable Clock Multiplier in 0.18-μm CMOS With -70 dBc Reference Spur," IEEE J. Solid -State Circuits, vol. 42, no. 8, pp. 1642-1648, Aug. 2007.
3. S. Ye and I. Galton, "Techniques for Phase Noise Suppression in Recirculating DLLs," IEEE J. Solid-State Circuits, vol. 39, no. 8, pp. 1222-1230, Aug. 2004.