A 0.5-5-GHz wide-range multiphase DLL with a calibrated charge pump

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 54, Issue 11, 2007, Pages 939-943

  Chuang, Chi Nan ^a   Liu, Shen Iuan ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Calibration; Charge pump; Delay locked loop; Multiperiod locked technique

Indexed keywords

CALIBRATION; CHARGE PUMP CIRCUITS;

CHARGE PUMP; CHARGE PUMP CURRENTS; DELAY-LOCKED LOOPS; INPUT FREQUENCY; MULTI-PERIOD; ROOT MEAN SQUARE; STATIC PHASE ERRORS; SUPPLY VOLTAGES;

DELAY LOCK LOOPS;

EID: 55649098872     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2007.904155     Document Type: Article

References (10)

1. G. Chien and P. R. Gray, "A 900 MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications," IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1995-1996, Dec. 2000.
2. H. H. Chang, J. W. Lin, C. Y. Yang, and S. I. Liu, "A wide range delay-locked loop with a fixed latency of one clock cycle," IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1021-1027, Aug. 2002.
3. A. Coban, M. H. Koroglu, and K. A. Ahmed, "A 2.5-3.125 GB/s quad transceiver with second order analog DLL-based CDRs," IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1940-1947, Sep. 2005.
4. C. N. Chuang and S. I. Liu, "A 40 GHz DLL-based clock generator in 90 nm CMOS technology," in Proc. Dig. Tech. Papers, ISSCC, Feb. 2007, pp. 178-179.
5. M.-J. E. Lee et al., "Jitter transfer characteristics of delay-locked," IEEE J. Solid-State Circuits, vol. 38, no. 4, pp. 614-621, Apr. 2003.
6. A. Maxim, "A 2-5 GHz low jitter 0.13 μm CMOS PLL using a dynamic current matching charge-pump and a noise attenuating loop-filter," in Proc. IEEE CICC, Oct. 2004, pp. 147-150.
7. W. S. T. Yan and H. C. Luong, "A 900-MHz CMOS low-phase-noise voltage-controlled ring oscillator," IEEE Trans. Circuits Syst. II. Exp. Briefs, vol. 48, no. 2, pp. 216-221, Feb. 2001.
8. K. Nakamura, M. Fukaishi, Y. Hirota, Y. Nakazawa, and M. Yotsuyanagi, "A CMOS 50% duty cycle repeater using complementary phase blending," in Proc. Dig. Tech. Papers, Symp. VLSI Circuits, Jun. 2000, pp. 48-49.
9. Q. Du, J. Zhuang, and T. Kwasniewski, "A low-phase noise, antiharmonic programmable DLL frequency multiplier with period error compensation for spur reduction," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 11, pp. 1205-1209, Nov. 2006.
10. B. G. Kim and L. S. Kim, "A 250 MHz-2-GHz wide-range delay-locked loop," IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1310-1321, Jun. 2005.