A 40GHz DLL-based clock generator in 90nm CMOS technology

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 178-180

  Chuang, Chi Nan ^a   Liu, Shen Iuan ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CLOCKS; ELECTRIC POWER UTILIZATION; PHASE SHIFT; TIMING JITTER;

CLOCK GENERATORS; MULTI-PHASE DLL; PEAK-TO-PEAK JITTER;

ELECTRIC GENERATORS;

EID: 34548813342     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373352     Document Type: Conference Paper

References (4)

1. G. Chien and P.R. Gray, "A 900MHz Local Oscillator Using a DLL-Based Frequency Multiplier Technique for PCS Applications," IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1995-1996, Dec., 2000.
2. H.H. Chang, J.W. Lin, C.Y. Yang, and S.I. Liu, "A Wide Range Delay-Locked Loop with a Fixed Latency of One Clock Cycle," IEEE J. Solid-State Circuits, vol. 37, no. 8, pp. 1021-1027, Aug., 2002.
3. K. Nakamura, M. Fukaishi, Y. Hirota, et al., "A CMOS 50% Duty Cycle Repeater Using Complementary Phase Blending," Symp. VLSI Circuits, pp. 48-49, Jun., 2000.
4. T.C. Lee and K.J. Hsiao, "The Design and Analysis of a DLL-Based Frequency Synthesizer for UWB Application," IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1245-1252, Jun., 2006.