Analysis of first-order anti-aliasing integration sampler

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 55, Issue 10, 2008, Pages 2994-3005

  Mirzaei, Ahmad ^a   Chehrazi, Saeed ^b   Bagheri, Rahim ^c   Abidi, Asad A ^b  

^a BROADCOM CORPORATION   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c Wilinx Inc   (United States)

Author keywords

Anti aliasing; Charge sampling; Impulse sampler; Integration sampler; Jitter; Noise; Receiver; Software defined radio (SDR)

Indexed keywords

ANALOG CIRCUITS; ANTI-ALIASING; CLOCKS; ELECTRIC RESISTANCE; INTEGRATION; JITTER; RADIO; RADIO RECEIVERS; RECEIVERS (CONTAINERS); TRANSCONDUCTANCE;

CHARGE SAMPLING; IMPULSE SAMPLER; INTEGRATION SAMPLER; NOISE; SOFTWARE-DEFINED RADIOS;

SOFTWARE RADIO;

EID: 57149127832     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2008.924127     Document Type: Article

References (27)

1. J. Mitola, "The software radio architecture," IEEE Commun. Mag., vol. 33, no. 5, pp. 26-38, May 1995.
2. A. V. Oppenheim, A. S. Willsky, and S. H. Nawab, Signals and Systems 2nd ed. Englewood Cliffs, NJ: Prentice-Hall, 1996.
3. Digital Cellular Telecommunications System (Phase 2+): Radio Transmission and Reception, Rev. 8.15.0, European Telecommunication Standard Inst. (ETSI), 1999.
4. D. Johns and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 1996.
5. R. H. Walden, "Analog-to-digital converter survey and analysis," IEEE J. Sel. Areas Commun., vol. 17, no. 4, pp. 539-550, Apr. 1999.
6. R. Bagheri, A. Mirzaei, S. Chehrazi, M. E. Heidari, M. Lee, M. Mikhemar, W. Tang, and A. A. Abidi, "An 800-MHz-6-GHz software-defined wireless receiver in 90-nm CMOS," IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2860-2876, Dec. 2006.
7. A. A. Abidi, "Evolution of a software-defined radio receiver's RF front-end," in Proc. IEEE RFIC Symp., San Francisco, CA, 2006, pp. 17-20.
8. S. J. Orfanidis, Introduction to Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, 1995.
9. Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specification, Further Higher-Speed Physical Layer Extension in the 2.4 GHz Band, IEEE Std. 802.11 g, 2002.
10. J. Yuan, "A charge sampling mixer with embedded filter function for wireless applications," in Proc. 2nd Int. Conf. Microw. Millimeter Wave Technol., Beijing, China, 2000, pp. 315-318.
11. Y. Poberezhskiy and G. Poberezhskiy, "Sampling and signal reconstruction structures performing internal antialiasing filtering and their influence on the design of digital recievers and transmitters," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 1, pp. 118-129, Jan. 2004.
12. T. L. Brooks, D. H. Robertson, D. F. Kelly, A. D. Muro, and S. W. Harston, "A 16 b sigma-delta pipeline ADC with 2.5 MHz output data-rate," in Int. Solid-State Circuits Conf. Tech. Dig., Feb. 1997, pp. 208-209.
13. C. Eichenberger and W. Guggenbuhl, "On charge injection in analog MOS switches and dummy switch compensation techniques," IEEE Trans. Circuits Syst., vol. 37, no. 2, pp. 256-264, Feb. 1990.
14. A. Mirzaei, R. Bagheri, S. Chehrazi, and A. A. Abidi, "A second-order anti-aliasing prefilter for an SDR receiver," in Proc. IEEE Custom Integrated Circuits Conf., Sep. 18-21, 2005, pp. 629-632.
15. A. Mirzaei, "Clock programmable IF circuits for CMOS software defined radio receiver and precise quadrature oscillators," Ph.D. dissertation, Dept. of Elect. Eng., Univ. of California, Los Angeles, 2006.
16. B. Razavi, Design of Analog CMOS Integrated Circuit. New York: McGraw-Hill, 2000.
17. D. Chen, W. Wang, and T. Kwasniewski, "Design considerations for a direct RF sampling mixer," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 11, pp. 934-938, Nov. 2007.
18. A. Dei and M. Valle, "Modelling charge injection in MOS analogue switches using a compact model in a deep submicron technology," in Proc. IEE Circuits, Devices Syst., Jun. 2006, vol. 153, pp. 268-272.
19. G. Wegmann, E. A. Vittoz, and F. Rahali, "Charge injection in analog MOS switches," IEEE J. Solid-State Circuits, vol. 22, no. 6, pp. 1091-1097, Dec. 1987.
20. J. Steensgaard, "Bootstrapped low-voltage analog switches," in Proc. Int. Symp. Circuits Syst., Orlando, FL, May 30-Jun. 2 1999, vol. 2, pp. 29-32.
21. A. M. Abo, "Design for reliability of low-voltage switched capacitor circuits," Ph.D. dissertation, Dept. Elect. Eng and Comput. Sci., Univ. of California, Berkeley, 1999.
22. R. B. Staszewski, K. Muhammad, D. Leipold, C.-M. Hung, Y.-C. Ho, J. L. Wallberg, C. Fernando, K. Maggio, R. Staszewski, T. Jung, J. Koh, S. John, I. Y. Deng, V. Sarda, O. Moreira-Tamayo, V. Mayega, R. Katz, O. Friedman, O. E. Eliezer, E. de Obaldia, and P. T. Balsara, "All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2278-2291, Dec. 2004.
23. K. Muhammad, Y. C. Ho, T. Mayhugh, C. M. Hung, T. Jung, I. Elahi, C. Lin, I. Deng, C. Fernando, J. Wallberg, S. Vemulapalli, S. Larson, T. Murphy, D. Leipold, P. Cruise, J. Jaehnig, M. C. Lee, R. B. Staszewski, R. Staszewski, and K. Maggio, "A discrete time quad-band GSM/GPRS receiver in a 90 nm digital CMOS process," in Proc. IEEE Custom Integrated Circuits Conf., Sep. 2005, pp. 809-812.
24. G. Xu and J. Yuan, "Performance analysis of general charge sampling," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 52, no. 2, pp. 107-111, Feb. 2005.
25. L. R. Cenkeramaddi and T. Ytterdal, "Jitter analysis of general charge sampling amplifiers," in Proc. Int. Symp. Circuits Syst., May 2006, pp. 5267-5270.
26. S. Karvonen, T. Riley, and J. Kostamovaara, "On the effects of timing Jitter in charge sampling," in Proc. Int. Symp. Circuits Syst., May 2003, vol. 1, pp. 737-740.
27. A. Demir, A. Mehrotra, and J. Roychowdhury, "Phase noise in oscillators: A Unifying theory and numerical methods for characterization," IEEE Trans. Circuits Syst. I, Analog Digit. Signal Process., vol. 47, no. 5, pp. 655-674, May 2000.