A second-order anti-aliasing prefilter for an SDR receiver

Proceedings of the Custom Integrated Circuits Conference

Volumn 2005, Issue , 2005, Pages 629-632

  Mirzaei, A ^a   Bagheri, R ^a   Chehrazi, S ^a   Abidi, A A ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACOUSTIC IMPEDANCE; BANDWIDTH; CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; SIGNAL RECEIVERS;

BLOCKERS; PREFILTERS; SAMPLE RATE;

DIGITAL FILTERS;

EID: 33847148081     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2005.1568748     Document Type: Conference Paper

References (4)

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2. R. B. Staszewski, et al., "All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS," IEEE J. of Solid-State Circuits, vol. 39, no. 12, pp. 2278-2291, 2004.
3. S. Karvonen, T. A. D. Riley, and J. Kostamovaara, "A CMOS Quadrature Charge-Domain Sampling Circuit With 66-dB SFDR Up to 100 MHz," IEEE Trans. on Circuits and Systems I, vol. 52, no. 2, pp. 292-304, 2005.
4. C. C. Enz and G. C. Temes, "Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization," Proc. of the IEEE, vol. 84, no. 11, pp. 1584-1614, 1996.