On the effects of timing jitter in charge sampling

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2003, Pages

  Karvonen, Sami ^a   Riley, Thomas ^a   Kostamovaara, Juha ^a  

^a UNIVERSITY OF OULU   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; INTEGRATED CIRCUITS; SIGNAL TO NOISE RATIO;

SAMPLING CIRCUITS;

TIMING JITTER;

EID: 0038489171     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. S.S. Awad: "Analysis of Accumulated Timing-Jitter in the Time Domain", IEEE Trans, on Inst. and Meas. Vol. 47, No. 1, February 1998.
2. M. Shinagawa et al.: "Jitter Analysis of High-Speed Sampling Systems", IEEE Journal of Solid-State Circ., Vol. 25, No. 1, February 1990.
3. S. Karvonen et al.: "A low noise quadrature subsampling mixer", Proc. of the ISCAS, Sydney, Australia, 2001.
4. th Inst. and Meas. Tech. Conf., Venice, Italy, 1999.
5. S. Karvonen et al.: "Charge sampling mixer with ΔΣ quantized impulse response", Proc. of the ISCAS, Scottsdale, Arizona, USA, 2002.