Accurate estimation of global buffer delay within a floorplan

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 6, 2006, Pages 1140-1146

  Alpert, Charles J ^a   Hu, Jiang ^b   Sapatnekar, Sachin S ^c   Sze, C N ^b  

^a IBM   (United States)

^b Texas AandM University   (United States)

^c UNIVERSITY OF MINNESOTA   (United States)

Author keywords

Delay estimation; Design automation; Integrated circuit interconnections; Integrated circuit layout; RC circuits; Repeaters; Very large scale integration

Indexed keywords

AUTOMATION; COMPUTER AIDED DESIGN; ESTIMATION; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; VLSI CIRCUITS;

DELAY ESTIMATION; DESIGN AUTOMATION; INTEGRATED CIRCUIT INTERCONNECTIONS; RC CIRCUITS;

DELAY CIRCUITS;

EID: 33646729462     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.855889     Document Type: Article

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