An LP-based methodology for improved timing-driven placement

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2, Issue , 2005, Pages 1139-1143

  Wang, Qingzhou ^a   Lillis, John ^a   Sanyal, Shubhankar ^a  

^a University of Illinois at Chicago   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUDGET CONTROL; COMPUTER AIDED DESIGN; LINEAR PROGRAMMING; TIMING CIRCUITS;

CLOCK PERIOD; OPTIMAL TIMING; SUB-CIRCUITS; TIMING DRIVEN PLACEMENT; TIMING-DRIVEN;

ITERATIVE METHODS;

EID: 84861444672     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1120725.1120925     Document Type: Conference Paper

References (10)

1. H. Eiscnmann and F. M. Johannes. Generic global placement and floor-pfanning. In Proceedings of the 35th annual conference on Design automation, pages 269-274, 1998.
2. M Hrkic;, J. Lillis, and G. Beraudo. An approach to placement-coupled logic replication. In Proceedings of the 41st annual conference on Design automation, pages 711-716, 2004.
3. S.-W. Hur and J. Lillis. Relaxation and clustering in a local search framework: application to linear placement. In Proceedings of the 36th ACM/IEEE conference on Design automation, pages 360-366, 1999.
4. S. W. Hur and J. Lillis. Mongrel: hybrid techniques for standard cell placement. In Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, pages 165-170, 2000.
5. M. A. B. Jackson and E. S. Kuh. Performance-driven placement of cell based ic's. In Proceedings of the 26th ACM/IEEE conference on Design automation, pages 370-375, 1989.
6. A. Marquardt, V. Betz, and J- Rose. Timing-driven placement for fpgas. In Proceedings of the 2000ACM/SIGDA eighth international symposium on Field programmable gate arrays, pages 203-213, 2000.
7. K. Rajagopal, T. Shaked, Y. Parasuram, T. Cao, A. Chowdhary, and B, Halpin. Timing driven force directed placement with physical net constraints. In Proceedings of the 2003 international symposium on Physical design, pages 60-66, 2003.
8. W. Swartz and C. Sechen. Timing driven placement for large standard cell circuits. In Proceedings of the 32nd ACM/IEEE conference on Design automation, pages 211-215, 1995.
9. http://www.eecg.toronco,edurvaughn/challenge/challenge.html
10. http://www.ilog.com/products/cplex/