Modeling the electrical effects of metal dishing due to CMP for on-chip interconnect optimization

IEEE Transactions on Electron Devices

Volumn 51, Issue 10, 2004, Pages 1577-1583

  Chang, Runzi ^a   Cao, Yu ^a   Spanos, Costas J ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL MECHANICAL POLISHING; COMPUTER SIMULATION; MATHEMATICAL MODELS; OPTIMIZATION; SCANNING ELECTRON MICROSCOPY;

CHEMICAL MECHANICAL PLANARIZATION (CMP); DAMASCENE PROCESS; DISHING RADIUS; LINE SPLITTING; METAL DISHING;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 5444255768     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.834898     Document Type: Article

References (18)

1. S. Sun, "Process technologies for advanced metallization and interconnect systems," in IEDM Tech. Dig., 1997, pp. 765-768.
2. H. Chen, T. Tsai, Y. Huang, C. Huang, C. Chen, Y. Wei, M. Yang, J. Wu, T. Yew, and J. Chen, "Defect reduction of copper BEOL for advanced ULSI interconnect," in IEEE Int. Interconnect Technology Conf., June 2001, pp. 21-23.
3. H. Goel and D. Dance, "Yield enhancement challenges for 90 nm and beyond," in IEEEI/SEMI Advanced Semiconductor Manufacturing Conf., Apr. 2003, pp. 262-265.
4. M. Gupta, G. Rajagopalan, C. Hong, J. Lu, K. Rose, and R. Gutmann, "Planarization yield limiters for wafer-scale 3D ICs," in IEEEI/SEMI Advanced Semiconductor Manufacturing Conf., May 2002, pp. 278-283.
5. B. Stine, D. Boning, J. Chung, L. Camilletti, F. Kruppa, E. Equi, W. Loh, S. Prasad, M. Muthukrishnan, D. Towery, M. Berman, and A. Kapoor, "The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes," IEEE Trans. Semiconduct Manufact., vol. 45, pp. 665-678, Mar. 1998.
6. D. Ouma, D. Boning, J. Chung, W. Easter, V. Saxena, S. Misra, and A. Crevasse, "Characterization and modeling of oxide chemical-mechanical polishing using planarization length and pattern density concepts," IEEE Trans. Semiconduct. Manufact., vol. 15, pp. 232-244, May 2002.
7. G. Zhang, H. Qian, Y. Xia, and D. Wu, "Minimize dishing effects during chemical mechanical planarization of copper damascene structures," in Int. Conf. Solid-State and Integrated-Circuit Technol., vol. 1, Oct. 2001, pp. 423-426.
8. V. Nguyen, P. Van Der Velden, R. Daamen, H. Van Kranenburg, and P. Woerlee, "Modeling of dishing for metal chemical mechanical polishing," in IEDM Tech. Dig., Dec. 2000, pp. 499-502.
9. D. Ouma, D. Boning, J. Chung, G. Shin, L. Olsen, and J. Clark, "An integrated characterization and modeling methodology for CMP dielectric planarization," in IEEE Int. Interconnect Technol. Conf., June 1998, pp. 67-69.
10. B. Stine, D. Ouma, R. Divecha, D. Boning, J. Chung, D. Hetherington, C. Harwoo, O. Nakagawa, and O. Soo-Young, "Rapid characterization and modeling of pattern-dependent variation in chemical-mechanical polishing," IEEE Trans. Semiconduct. Manufact., vol. 11, pp. 129-140, Feb. 1998.
11. R. Tian, D. Wong, and R. Boone, "Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability," IEEE Trans. Computer-Aided Design, vol. 20, pp. 902-910, July 2001.
12. R. Tian, X. Tang, and D. Wong, "Dummy-feature placement for chemical-mechanical polishing uniformity in a shallow-trench isolation process," IEEE Trans. Computer-Aided Design, vol. 21, pp. 63-71, Jan. 2002.
13. S. Smith, A. Walton, A. Ross, G. Bodammer, and J. Stevenson, "Evaluation of sheet resistance and electrical line width measurement techniques for copper damascene interconnect," IEEE Trans. Semiconduct. Manufact., vol. 15, pp. 214-222, May 2002.
14. J. M. Steigerwald, S. P. Murarka, and R. J. Gutmann, Chemical Mechanical Planarization of Microelectronic Materials, New York: Wiley, 1997.
15. R. Chang, A. Jindal, R. Gutmann, and C. Spanos, "Copper chemical-mechanical polishing process modeling using the dishing radius concept," in Chemical-Mechanical Planarization 2003: 8th Annu. Int. Conf., Sept. 2003.
16. H. B. Bakoglu, Circuit, Interconnections, and Packaging for VLSI. Reading, PA: Addison-Wesley, 1990.
17. S. Wong, G. Lee, and D. Ma, "Modeling of interconnect capacitance, delay, and crosstalk in VLSI," IEEE Trans. Semiconduct. Manufact., vol. 13, pp. 108-111, Feb. 2000.
18. T. Chiang, K. Banerjee, and K. Saraswat, "Compact modeling and SPICE-based simulation for electro-thermal analysis of multilevel ULSI interconnects," in IEEE/ACM Int. Conf. Computer-Aided Design, Nov. 2001, pp. 165-172.