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IEEE International Symposium on Semiconductor Manufacturing Conference, Proceedings

Volumn , Issue , 2002, Pages 278-283

Planarization yield limiters for wafer-scale 3D ICs

(6) Gupta, M a Rajagopalan, G a Hong, C K a Lu, J Q a Rose, K a Gutmann, R J a

a RENSSELAER POLYTECHNIC INSTITUTE (United States)

Author keywords

3D ICs; CMP; Global planarity; Test structure; Yield

Indexed keywords

CHEMICAL VAPOR DEPOSITION; CHIP SCALE PACKAGES; MICROELECTRONIC PROCESSING; MONOLITHIC INTEGRATED CIRCUITS; THREE DIMENSIONAL; TWO DIMENSIONAL; WSI CIRCUITS;

CHEMICAL-MECHANICAL PLANARIZATION; PLANARIZATION YIELD LIMITERS; THREE DIMENSIONAL INTEGRATED CIRCUITS; THREE DIMENSIONAL PROCESSING; TWO DIMENSIONAL PROCESSING;

INTEGRATED CIRCUIT TESTING;

EID: 0036076323 PISSN: 1523553X EISSN: None Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper

Times cited : (2)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.