An integrated characterization and modeling methodology for CMP dielectric planarization

Proceedings of the IEEE 1998 International Interconnect Technology Conference, IITC 1998

Volumn 1998-June, Issue , 1998, Pages 67-69

  Ouma, D ^a   Boning, D ^a   Chung, J ^a   Shin, G ^b   Olsen, L ^b   Clark, J ^b  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FORECASTING;

CHARACTERIZATION METHODS; CHIP-LEVEL; METAL STRUCTURES; MODEL CALIBRATION; MODEL-PARAMETER EXTRACTION; MODELING METHODOLOGY; OXIDE THICKNESS; PLANARIZATION;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 78650728947     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.1998.704753     Document Type: Conference Paper

References (6)

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2. Y. Hayashide, M. Matsuura, M. Hirayama, T. Sasaki, S. Harada, H. Kotani, Proc. VIMIC Conf, pp. 464-47, Santa Clara, CA, June 1995.
3. H. Takahashi, K. Tokunaga, T. Kasuga, T. Suzuki, 7997 Symp. on VLSI Tech., pp. 25-26, Kyoto, Japan, 1997.
4. B. Stine et al., Proc. CMP-MIC Conf., Santa Clara, CA, Feb. 1997.
5. R. Divecha et al., Proc. CMP-MIC Conf., Santa Clara, CA, Feb. 1997.
6. F. W. Preston, J. Soc. Glass Tech., XI, 214, 1927.