Characteristics of different structure sub-100nm MOSFETs with high-k gate dielectrics

2001 6th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2001 - Proceedings

Volumn 1, Issue , 2001, Pages 333-336

  Liu, Xiaoyan ^a   Lou, Shuzuo ^a   Xia, Zhiliang ^a   Guo, Dechao ^a   Zhu, Huiwen ^a   Kang, Jinfeng ^a   Han, Ruqi ^a  

^a PEKING UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84966628881     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSICT.2001.981488     Document Type: Conference Paper

References (5)

1. Yuan Tuar, Douglas A. Buchanan, et. al. CMOS Scaling into the Nanometer Regime', Proceedings of IEEE, 85(4), 486,1997
2. Inani, V.R.Rao, B.cheng, M.Cao, P.V.Voorde, W.Greeene and J.C.S.Woo, Performance considerations in using high-K dielectric for deep sub-micron MOSFET's, Ext. Abstr. SSDM'98, 308, 1998
3. Bahong Cheng, Min Cao, Pamgoal Rao, Anand Inani, Paul Vande Voorde, Wayne M. Greene, Johannes M.C. Stork, Zhiping Yu, Peter M. Zeitzoff, Jason C.S.Woo, The impact of high-K gate dielectric and metal gate electrodes on sub-100nm MOSFET's. IEEE Trans. on Electron Devices, 46(7), 1537, 1999
4. G.C.F. Yeap, S.Krishnan, Fring-induced barrier lowering (FIBL) in sub-100nm MOSFETs with high-K gate dielectrics. Electronics Letters, 34(11), 1150, 1998
5. National technology roadmap for semiconductors. 1997 edition, SIA, San Jose, CA,USA