-
1
-
-
53349152753
-
-
The LLVM Compiler Infrastructure. Home page
-
The LLVM Compiler Infrastructure. Home page: http://llvm.cs.uiuc.edu/.
-
-
-
-
2
-
-
0036469652
-
Simplescalar: An infrastructure for computer system modeling
-
Feb
-
T. Austin, E. Larson, and D. Ernst. Simplescalar: An infrastructure for computer system modeling. IEEE Computer, 35(2):59-67, Feb. 2002.
-
(2002)
IEEE Computer
, vol.35
, Issue.2
, pp. 59-67
-
-
Austin, T.1
Larson, E.2
Ernst, D.3
-
3
-
-
0033321638
-
DIVA: A reliable substrate for deep submicron microarchitecture design
-
T. M. Austin. DIVA: A reliable substrate for deep submicron microarchitecture design. In Proc. of the Intl. Symp. on Microarchitecture, pages 196-207, 1999.
-
(1999)
Proc. of the Intl. Symp. on Microarchitecture
, pp. 196-207
-
-
Austin, T.M.1
-
5
-
-
0041633858
-
Parameter variations and impact on circuits and microarchitecture
-
S. Borkar et al. Parameter variations and impact on circuits and microarchitecture. In Proc. of the Annual Conf. on Design Automation, pages 338-342, 2003.
-
(2003)
Proc. of the Annual Conf. on Design Automation
, pp. 338-342
-
-
Borkar, S.1
-
7
-
-
0030286383
-
A gate-level simulation environment for alpha-particle-induced transient faults
-
Nov
-
H. Cha, E. M. Rudnick, J. H. Patel, R. K. Iyer, and G. S. Choi. A gate-level simulation environment for alpha-particle-induced transient faults. IEEE Trans. on Computers, 45(11):1248-1256, Nov. 1996.
-
(1996)
IEEE Trans. on Computers
, vol.45
, Issue.11
, pp. 1248-1256
-
-
Cha, H.1
Rudnick, E.M.2
Patel, J.H.3
Iyer, R.K.4
Choi, G.S.5
-
9
-
-
84944408150
-
Razor: A low-power pipeline based on circuit-level timing speculation
-
D. Ernst, N. S. Kim, S. Das, S. Pant, R. Rao, T. Pham, C. Zeisler, D. Blaauw, T. Austin, K. Flautner, and T. Mudge. Razor: A low-power pipeline based on circuit-level timing speculation. In Proc. of the Intl. Symp. on Microarchitecture, pages 7-18, 2003.
-
(2003)
Proc. of the Intl. Symp. on Microarchitecture
, pp. 7-18
-
-
Ernst, D.1
Kim, N.S.2
Das, S.3
Pant, S.4
Rao, R.5
Pham, T.6
Zeisler, C.7
Blaauw, D.8
Austin, T.9
Flautner, K.10
Mudge, T.11
-
11
-
-
0038346239
-
Transient-fault recovery for chip multiprocessors
-
M. Gomaa, C. Scarbrough, T. N. Vijaykumar, and I. Pomeranz. Transient-fault recovery for chip multiprocessors. In Proc. of the Intl. Symp. on Computer architecture, pages 98-109, 2003.
-
(2003)
Proc. of the Intl. Symp. on Computer architecture
, pp. 98-109
-
-
Gomaa, M.1
Scarbrough, C.2
Vijaykumar, T.N.3
Pomeranz, I.4
-
14
-
-
0029256045
-
FERRARI: A flexible software-based fault and error injection system
-
Feb
-
G. A. Kanawati, N. A. Kanawati, and J. A. Abraham. FERRARI: A flexible software-based fault and error injection system. IEEE Trans. on Computers, 44(2):248-260, Feb. 1995.
-
(1995)
IEEE Trans. on Computers
, vol.44
, Issue.2
, pp. 248-260
-
-
Kanawati, G.A.1
Kanawati, N.A.2
Abraham, J.A.3
-
18
-
-
15044363155
-
Robust system design with built-in soft-error resilience
-
Feb
-
S. Mitra, N. Seifert, M. Zhang, Q. Shi, and K. S. Kim. Robust system design with built-in soft-error resilience. IEEE Computer, 38(2):43-52, Feb. 2005.
-
(2005)
IEEE Computer
, vol.38
, Issue.2
, pp. 43-52
-
-
Mitra, S.1
Seifert, N.2
Zhang, M.3
Shi, Q.4
Kim, K.S.5
-
19
-
-
84944403418
-
A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor
-
S. S. Mukherjee, C. Weaver, J. Emer, S. K. Reinhardt, and T. Austin. A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor. In Proc. of the Intl. Symp. on Microarchitecture, pages 29-40, 2003.
-
(2003)
Proc. of the Intl. Symp. on Microarchitecture
, pp. 29-40
-
-
Mukherjee, S.S.1
Weaver, C.2
Emer, J.3
Reinhardt, S.K.4
Austin, T.5
-
20
-
-
27544441280
-
Microprocessor sensitivity to failures: Control vs. execution and combinational vs. sequential logic
-
June
-
G. P. Saggese, A. Vetteth, Z. Kalbarczyk, and R. Iyer. Microprocessor sensitivity to failures: control vs. execution and combinational vs. sequential logic. In Proc. of the Intl. Conf. on Dependable Systems and Networks, pages 760-769, June 2005.
-
(2005)
Proc. of the Intl. Conf. on Dependable Systems and Networks
, pp. 760-769
-
-
Saggese, G.P.1
Vetteth, A.2
Kalbarczyk, Z.3
Iyer, R.4
-
21
-
-
0036931372
-
Modeling the effect of technology trends on the soft error rate of combinational logic
-
June
-
P. Shivakumar, M. Kistler, S. W. Keckler, D. Burger, and L. Alvisi. Modeling the effect of technology trends on the soft error rate of combinational logic. In Proc. of the Intl. Conf. on Dependable Systems and Networks, pages 389-398, June 2002.
-
(2002)
Proc. of the Intl. Conf. on Dependable Systems and Networks
, pp. 389-398
-
-
Shivakumar, P.1
Kistler, M.2
Keckler, S.W.3
Burger, D.4
Alvisi, L.5
-
22
-
-
12844278588
-
Fingerprinting: Bounding soft-error detection latency and bandwidth
-
J. C. Smolens, B. T. Gold, J. Kim, B. Falsafi, J. C. Hoe, and A. G. Nowatzyk. Fingerprinting: bounding soft-error detection latency and bandwidth. In Proc. of the Intl. Conf. on Architectural Support for Programming Languages and Operating Systems, pages 224-234, 2004.
-
(2004)
Proc. of the Intl. Conf. on Architectural Support for Programming Languages and Operating Systems
, pp. 224-234
-
-
Smolens, J.C.1
Gold, B.T.2
Kim, J.3
Falsafi, B.4
Hoe, J.C.5
Nowatzyk, A.G.6
-
25
-
-
53349156199
-
Reliability requirements of control, address, and data operations in error-tolerant applications
-
D. D. Thaker, D. Franklin, V. Akella, and F. T. Chong. Reliability requirements of control, address, and data operations in error-tolerant applications. In Proc. of the Workshop on Architectural Reliability, 2005.
-
(2005)
Proc. of the Workshop on Architectural Reliability
-
-
Thaker, D.D.1
Franklin, D.2
Akella, V.3
Chong, F.T.4
-
26
-
-
84968854658
-
Y-branches: When you come to a fork in the road, take it
-
N. Wang, M. Fertig, and S. Patel. Y-branches: When you come to a fork in the road, take it. In Proc. of the Intl. Conf. on Parallel Architectures and Compilation Techniques, page 56, 2003.
-
(2003)
Proc. of the Intl. Conf. on Parallel Architectures and Compilation Techniques
, pp. 56
-
-
Wang, N.1
Fertig, M.2
Patel, S.3
-
28
-
-
4544282186
-
Characterizing the effects of transient faults on a high-performance processor pipeline
-
June
-
N. J. Wang, J. Quek, T. M. Rafacz, and S. J. Patel. Characterizing the effects of transient faults on a high-performance processor pipeline. In Proc. of the Intl. Conf. on Dependable Systems and Networks, pages 61-70, June 2004.
-
(2004)
Proc. of the Intl. Conf. on Dependable Systems and Networks
, pp. 61-70
-
-
Wang, N.J.1
Quek, J.2
Rafacz, T.M.3
Patel, S.J.4
|