Characterizing and predicting value degree of use

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn 2002-January, Issue , 2002, Pages 15-26

  Butts, J Adam ^a   Sohi, Gurindar S ^a  

^a University of Wisconsin Madison   (United States)

Author keywords

Bandwidth; Computational modeling; Computer science; Delay; Design optimization; Logic; Parallel processing; Prediction algorithms; Predictive models; Registers

Indexed keywords

ALGORITHMS; BANDWIDTH; COMPUTATION THEORY; COMPUTER ARCHITECTURE; COMPUTER SCIENCE; FORECASTING;

COMPUTATIONAL MODEL; DELAY; DESIGN OPTIMIZATION; LOGIC; PARALLEL PROCESSING; PREDICTION ALGORITHMS; PREDICTIVE MODELS; REGISTERS;

OPTIMIZATION;

EID: 52649105698     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2002.1176235     Document Type: Conference Paper

References (8)

1. D. Burger and T. Austin. The SimpleScalar tool set, version 2. 0. Technical Report CS-TR-97-1342, University of Wisconsin-Madison, June 1997.
2. J. Adam Butts and G. Sohi. Dynamic dead-instruction detection and elimination. In Proc. of the 10th Int'l Conf. on Architectural Support for Programming Languages and Operating Systems, October 2002. pp. 199-211.
3. J. Cruz, A. Gonzalez, M. Valero, and N. Topham. Multiple-banked register file architectures. In Proc. of the 27th Annual Int'l Symp. on Computer Architecture, June 2000. pp. 316-25.
4. L. Eeckhout and K. Bosschere. Hybrid analytical-statistical modeling for efficiently exploring architecture and workload design spaces. In Proc. of the 2001 Int'l Conf. on Parallel Architectures and Compilation Techniques, September 2001. pp. 25-34.
5. M. Franklin and G. Sohi. Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors. In Proc. of the 25th Int'l Symp. on Microarchitecture, December 1992. pp. 236-45.
6. H. Kim and J. Smith. An instruction set and microarchitecture for instruction level distributed processing. In Proc. of the 29th Annual Int'l Symp. on Computer Architecture, May 2002. pp. 71-81.
7. S. Palacharla, N. Jouppi, and J. E. Smith. Complexityeffective superscalar processors. In Proc. of the 24th Int'l Symp. on Computer Architecture, June 1997. pp. 206-18.
8. J. Philips and S. Vassiliadis. High performance 3-1 interlock collapsing ALUs. In IEEE Trans. on Computers, vol. 43, March 1994. pp. 257-68.