DFT techniques for memory macro with built-in ECC

Records of the IEEE International Workshop on Memory Technology, Design and Testing

Volumn , Issue , 2005, Pages 109-114

  Kushida, Keiichi ^a   Otsuka, Nobuaki ^a   Hirabayashi, Osamu ^a   Takeyama, Yasuhisa ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; CODES (SYMBOLS); COMPUTER HARDWARE; MATRIX ALGEBRA; PROBABILITY DENSITY FUNCTION;

ECC SYSTEM; HARDWARE CHARACTERIZATION; MEMORY MACRO;

STATIC RANDOM ACCESS STORAGE;

EID: 28344435918     PISSN: 10874852     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. P. Ramanathan, K.K. Saluja, M. Franklin, "Zero cost testing of check-bits in RAMs with on-chip ECC," VLSI Test Symposium, pages 292-297, Apr. 1992.
2. P. Ramanathan, K.K. Saluja, M. Franklin, "Testing check-bits at no cost in RAMs with on-chip ECC," Computers and Digital Techniques, IEE Proceedings E, vol. 140 Issue 6, Nov. 1993.
3. E.Q. Garcia, S.M. Paranjape, "Soft Error Correction Technique And System For Odd Weighted Row Error Correction Codes," IBM, U. S. patent no. 5644583
4. G. Nagano, M. Takahashi, "Error-Correcting System," Fujitsu, U.S. patent 4394763
5. L. Penzo et al., "VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes," in Proc. 8th Int. Conf. on VLSI Design, Jan. 1995.