Impact of the gate stack on the electrical performances of 3D Multi-Channel MOSFET (MCFET) on SOI

ESSDERC 2007 - Proceedings of the 37th European Solid-State Device Research Conference

Volumn 2007, Issue , 2007, Pages 147-150

  Bernard, E ^a,b,c   Ernst, T ^a   Guillaumot, B ^b   Vulliet, N ^b   Garros, X ^a   Maffini Alvaro, V ^a   Andrieu, F ^a   Barral, V ^a   Allain, F ^a   Toffoli, A ^a   Vidal, V ^b   Delaye, V ^a   Vizioz, C ^a   Campidelli, Y ^b   Kermarrec, O ^b   Hartmann, J M ^a   Borel, S ^a   Faynot, O ^a   Souifi, A ^c   Coronel, P ^b   Skotnicki, T ^b   Deleonibus, S ^a   more..

^a CEA LETI   (France)

^b STMICROELECTRONICS   (France)

^c INSTITUT DES NANOTECHNOLOGIES DE LYON   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON MOBILITY; GATE DIELECTRICS; HOLE MOBILITY; LEAKAGE CURRENTS; SILICON ON INSULATOR TECHNOLOGY;

GATE STACK; NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI);

MOSFET DEVICES;

EID: 39549113174     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2007.4430900     Document Type: Conference Paper

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