In-depth analysis of 4T SRAM cells in double-gate CMOS

Proceedings 2007 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT

Volumn , Issue , 2007, Pages 246-249

  Giraud, Bastien ^b   Vladimirescu, Andrei ^c   Amara, Amara ^a,b  

^a IEEE

^b Institut Superieur d'Electronique de Paris ISEP   (France)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Fully depleted double gate technology; Memory SRAM cells; Static noise margin; Write disturb

Indexed keywords

CELLS; CMOS INTEGRATED CIRCUITS; DATA STORAGE EQUIPMENT; ENERGY STORAGE; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; MOSFET DEVICES; NONMETALS; SILICON; STATIC RANDOM ACCESS STORAGE; TECHNOLOGY;

4T SRAM; ACCESS TIME; BACK GATES; DOUBLE GATE (DG); FULLY-DEPLETED (FD); GATE OPERATIONS; IN DEPTH ANALYSIS; INTEGRATED CIRCUIT (IC) DESIGN; INTERNATIONAL CONFERENCES; OPERATING MARGINS; PROCESS VARIATIONS; SELF ALIGNED (SA); SILICON ON INSULATOR (SOI) TECHNOLOGY; SRAM CELLS; WRITE MARGINS;

SILICON ON INSULATOR TECHNOLOGY;

EID: 47349096207     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICICDT.2007.4299583     Document Type: Conference Paper

References (8)

1. M. Yamaoka et al., "Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell technology", Symp. VLSI Circuits Dig. 18, pp. 288-291, 2004.
2. Z. Guo, Sriram Balasubramanian, Radu Zlatanovici, Tsu-Jae King and Borivoje Nikolic, "FinFET-based SRAM design", UC Berkeley, ISLPED, San Diego, California, USA, 2005.
3. W. Leung and F. C. Hsu, "High-density ratio-independent four-transistor RAM cell fabricated with a conventional logic process", US Patent, NO. 6 44 060 B1, Monolithic system technology, 2002.
4. M. Vinet et al., "Bonded planar double-metal-gate NMOS transistors down to 10 nm", IEEE Electron Devices Let., vol. 26, No. 5, p. 317-319, 2005.
5. H. Qin, Yu Cao, Dejan Markovic, Andrei Vladimirescu and Jan Rabaey, "Standby supply voltage minimization for deep sub-micron SRAM", Microelectron. J. 36, No. 9, 789800, 2005.
6. O. Thomas and A. Amara, "An SOI 4 transistors self-refresh ultra-low-voltage memory cell", ISCAS, Thailand Bangkok 2003.
7. E. Seevinck Sr., F. J. List and J. Lohstroh, "Static-noise margin analysis of MOS SRAM cells", IEEE Journal of Solid-State Circuits, vol. 22, pp. 748-754, 1987.
8. M. Reyboz, T. Poiroux, 0. Rozeau, P. Martin and J. Jomaah, "Explicit threshold voltage based compact model of independent double gate (IDG) MOSFET including short channel effects", CEA, Grenoble.