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Volumn , Issue , 2005, Pages 42-46

Electrical and topological characterization of interconnect open defects

Author keywords

[No Author keywords available]

Indexed keywords

ATTENUATION; ELECTRIC POWER SYSTEM INTERCONNECTION; ELECTRIC PROPERTIES; ERROR ANALYSIS; PHASE SHIFT; TIME DOMAIN ANALYSIS; TOPOLOGY;

EID: 33749060217     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DBT.2005.1531300     Document Type: Conference Paper
Times cited : (7)

References (8)
  • 4
    • 84948428485 scopus 로고    scopus 로고
    • Fault models for speed failures caused by bridges and opens
    • Proceedings 20th IEEE, May
    • Chakravarty, S.; Jain, A.; "Fault models for speed failures caused by bridges and opens", VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE, pp. 373 - 378, May 2002.
    • (2002) VLSI Test Symposium, 2002. (VTS 2002) , pp. 373-378
    • Chakravarty, S.1    Jain, A.2
  • 5
    • 3142664872 scopus 로고    scopus 로고
    • New test methodology for resistive open defect detection in memory address decoders
    • Proceedings. IEEE
    • Azimane, M.; Majhi, A.K.; "New test methodology for resistive open defect detection in memory address decoders", VLSI Test Symposium, 2004. Proceedings. IEEE, pp. 123-128, 2004.
    • (2004) VLSI Test Symposium, 2004 , pp. 123-128
    • Azimane, M.1    Majhi, A.K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.