A 2.5 GHz all-digital delay-locked loop in 0.13 μm CMOS technology

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 11, 2007, Pages 2338-2347

  Yang, Rong Jyi ^a,b   Liu, Shen Iuan ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b CHANG GUNG UNIVERSITY   (Taiwan)

Author keywords

All digital; Delay locked loop; Modified successive approximation register; tri state phase detector

Indexed keywords

ALL-DIGITAL; CLOSED LOOPS; CMOS TECHNOLOGIES; DELAY STEPS; DELAY UNITS; DELAY-LOCKED LOOP; DIGITAL DELAY-LOCKED LOOPS; INTRINSIC DELAYS; LOAD VARIATIONS; MODIFIED SUCCESSIVE APPROXIMATION REGISTER; NAND GATES; PEAK-TO-PEAK JITTER; TRI-STATE PHASE DETECTOR;

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; DETECTORS; JITTER; PHASE LOCKED LOOPS; SIGNAL DETECTION;

ANTENNA PHASED ARRAYS;

EID: 51549085189     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.906183     Document Type: Conference Paper

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