Jitter transfer characteristics of delay-locked loops - Theories and design techniques

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 4, 2003, Pages 614-621

  Lee, M J Edward ^a   Dally, William J ^a,b   Greer, Trey ^a   Ng, Hiok Tiaq ^a   Farjad Rad, Ramin ^a   Poulton, John ^a   Senthinathan, Ramesh ^a  

^a Velio Communications Inc   (United States)

^b Stanford University   (United States)

Author keywords

Delay locked loop (DLL); Injection locking; Jitter peaking; Jitter transfer; Multiplying delay locked loop (MDLL); Phase locked loop (PLL)

Indexed keywords

AMPLIFICATION; BANDWIDTH; JITTER; MATHEMATICAL MODELS; SIGNAL FILTERING AND PREDICTION; TIMING CIRCUITS;

DELAY LOCKED LOOPS; JITTER TRANSFER; LOOP FILTERING; PHASE FILTERING; Z-DOMAIN MODEL;

PHASE LOCKED LOOPS;

EID: 0037387774     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.809519     Document Type: Article

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