Asynchronous Data Path Models

Proceedings - 7th International Conference on Application of Concurrency to System Design, ACSD 2007

Volumn , Issue , 2007, Pages 197-210

  Sokolov, Danil ^a   Poliakov, Ivan ^a   Yakovlev, Alex ^a  

^a NEWCASTLE UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SOFTWARE; DECODING; GRAPH THEORY; INFORMATION THEORY; MARINE BIOLOGY; PETRI NETS; SEMANTICS; SYSTEMS ANALYSIS;

(EXTENDED) PETRI NETS; ASYNCHRONOUS DATA PATH; COUNTER FLOWS; GAME SEMANTICS; INTERNATIONAL CONFERENCES; MODEL-CHECKING TOOLS; SOFTWARE TOOLS; SYSTEM DESIGNS;

MODEL CHECKING;

EID: 51149112285     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ACSD.2007.45     Document Type: Conference Paper

References (24)

1. Manoj Ampalam and Montek Singh. Counterflow pipelining: architectural support for preemption in asynchronous systems using anti-tokens. In Proc. International Conference Computer-Aided Design (ICCAD), November 2006.
2. John Bainbridge, W.B. Toms, Doug Edwards, and Steve Furber. Delay-insensitive, point-to-point interconnect using M-of-N codes. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), pages 132-140. IEEE Computer Society Press, May 2003.
3. Ivan Blunno and Luciano Lavagno. Automated synthesis of micro-pipelines from behavioral Verilog HDL. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), pages 84-92. IEEE Computer Society Press, April 2000.
4. Ivan Blunno and Luciano Lavagno. Designing an asynchronous microcontroller using Pipefitter. In Proc. International Conference Computer Design (ICCD), 2002.
5. Charles Brej. Early output logic and anti-tokens. PhD thesis, Dept. of Computer Science, University of Manchester, 2005.
6. Charles Brej and Jim Garside. Early output logic using anti-tokens. In Proc. International Workshop on Logic Synthesis, pages 302-309. ACM Press, May 2003.
7. Alex Bystrov, Danil Sokolov, and Alex Yakovlev. Low-latency control structures with slack. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), pages 164-173. IEEE Computer Society Press, May 2003.
8. Wei-Chun Chou, Peter A. Beerel, and Kenneth Y. Yun. Average-case technology mapping of asynchronous burst-mode circuits. IEEE Transactions on Computer-Aided Design, 18(10):1418-1434, October 1999.
9. Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, and Alex Yakovlev. Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers. IE-ICE Transactions on Information and Systems, E80-D(3):315-325, March 1997.
10. A. Dindhuc, J.-B. Rigaud, A. Rezzag, A. Sirianni, João Loenardo Fragoso, L. Fesquet, and Marc Renaudin. Tima asynchronous synthesis tools. In Communication to ACID Worshop, January 2002.
11. R. M. Fuhrer, Steven M. Nowick, Michael Theobald, N. K. Jha, B. Lin, and Luis Plana. Minimalist: an environment for the synthesis, verification and testability of burst-mode asynchronous machines. Technical Report TR CUCS-020-99, Columbia University, July 1999.
12. Victor Khomenko. Model checking based on Petri net unfolding prefixes. PhD thesis, School of Computer Science, University of Newcastle upon Tyne, 2002.
13. Michael Kishinevsky, Alex Kondratyev, Alexander Taubin, and Victor Varshavsky. Concurrent hardware: the theory and practice of self-timed design. Series in Parallel Computing. Wiley-Interscience, John Wiley& Sons, Inc., 1994.
14. Alex Kondratyev and Kelvin Lwin. Design of asynchronous circuits using synchronous CAD tools. IEEE Design & Test of Computers, 19(4): 107-117, 2002.
15. Carl Adam Petri. Kommunikation mit automaten (Communicating with automata). PhD thesis, University of Bonn, 1962.
16. Delong Shang, Frank Burns, Albert Koelmans, Alex Yakovlev, and F. Xia. Asynchronous system synthesis based on direct mapping using VHDL and Petri nets. IEE Proceedings, Computers and Digital Techniques, 151(3):209-220, May 2004.
17. Danil Sokolov, Julian P. Murphy, Alex Bystrov, and Alex Yakovlev. Design and analysis of dual-rail circuits for security applications. IEEE Transactions on Computers, 54(4):449-460, April 2005.
18. Jens Sparsø and Steve Furber. Principles of asynchronous circuit design: a system perspective. Kluwer Academic Publishers, 2001.
19. Robert F. Sproull, Ivan E. Sutherland, and Charles E. Moinar. The counterflow pipeline processor architecture. IEEE Design & Test of Computers, 11(3):48-59, 1994.
20. W.B.Toms. Synthesis of quasi-delay-insensitive data-path circuits. PhD thesis, Dept. of Computer Science, University of Manchester, 2006.
21. Walter Vogler and Ralf Wollowski. Decomposition in asynchronous circuit design. In Jordi Cortadella, Alex Yakovlev, and Grzegorz Rozenberg, editors, Concurrency and Hardware Design, volume 2549 of Lecture Notes in Computer Science, pages 152-190. Springer-Verlag, 2002.
22. Alex Yakovlev, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, and Marta Pietkiewicz-Koutny. On the models for asynchronous circuit behaviour with OR causality. Formal Methods in System Design, 9:189-233, 1996.
23. T. Yoneda, H. Onda, and Chris J. Myers. Synthesis of speed independent circuits based on decomposition. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC), pages 135-145. IEEE Computer Society Press, April 2004.
24. Yu Zhou, Danil Sokolov, and Alex Yakovlev. Costaware synthesis of asynchronous circuit. In Proc. International Conference Computer-Aided Design (ICCAD), November 2006.