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Volumn , Issue , 2003, Pages 164-173

Low-latency control structures with slack

Author keywords

[No Author keywords available]

Indexed keywords

MERGING;

EID: 77957967409     PISSN: 26431394     EISSN: 26431483     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.2003.1199176     Document Type: Conference Paper
Times cited : (7)

References (31)
  • 1
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    • A. Allan, et. al. 2001 Technology Roadmap for Semiconductors, Computer, January 2002.
    • (2001) Computer
    • Allan, A.1
  • 9
    • 0012022507 scopus 로고
    • ASSASSIN: A synthesis system for asynchronous control circuits
    • Design Methodologies for VLSI Systems Division, Leuven, Belgium
    • C. Ykman-Couvreur, B. Lin, H. De Man. ASSASSIN: A Synthesis System for Asynchronous Control Circuits. IMEC, 1995, Design Methodologies for VLSI Systems Division, Leuven, Belgium.
    • (1995) IMEC
    • Ykman-Couvreur, C.1    Lin, B.2    De Man, H.3
  • 11
    • 0020310934 scopus 로고
    • Direct implementation of asynchronous control units
    • Dec.
    • A. L. Hollaar. Direct Implementation of Asynchronous Control Units. IEEE Transactions on Computers, C-31, No 12, Dec. 1982, pp. 1133-1141.
    • (1982) IEEE Transactions on Computers , vol.C-31 , Issue.12 , pp. 1133-1141
    • Hollaar, A.L.1
  • 13
    • 33745491925 scopus 로고    scopus 로고
    • Asynchronous circuit synthesis by direct mapping: Interfacing to environment
    • April Manchester
    • A. Bystrov and A. Yakovlev, Asynchronous Circuit Synthesis by Direct Mapping: Interfacing to Environment, Proc. ASYNC2002, April, 2002, Manchester.
    • (2002) Proc. ASYNC 2002
    • Bystrov, A.1    Yakovlev, A.2
  • 14
    • 27944452405 scopus 로고    scopus 로고
    • Synthesis of asynchronous circuits with predictable latency
    • University of Newcastle accepted to 1 WLS-02, New Orleans, June
    • A. Bystrov, A. Yakovlev, Synthesis of Asynchronous Circuits with Predictable Latency, CS-TR-754, Department of Computing Science, University of Newcastle, 2001; accepted to 1WLS-02, New Orleans, June 2002.
    • (2001) CS-TR-754, Department of Computing Science
    • Bystrov, A.1    Yakovlev, A.2
  • 16
    • 0036173333 scopus 로고    scopus 로고
    • Balsa: An asynchronous hardware synthesis language
    • D. Edwards and A. Bardsley. Balsa: An Asynchronous Hardware Synthesis Language. The Computer Journal, vol. 45, 2002, pp. 12-18.
    • (2002) The Computer Journal , vol.45 , pp. 12-18
    • Edwards, D.1    Bardsley, A.2
  • 20
    • 25644445892 scopus 로고
    • A unified STG model for asynchronous control circuit synthesis
    • Santa Clara, CA, Nov.
    • A. Yakovlev, L. Lavagno, A. Sangovanni-Vincentelli. A Unified STG Model for Asynchronous Control Circuit Synthesis. In Proc. ICCAD'92, Santa Clara, CA, Nov. 1992.
    • (1992) Proc. ICCAD'92
    • Yakovlev, A.1    Lavagno, L.2    Sangovanni-Vincentelli, A.3
  • 26
    • 51249086385 scopus 로고    scopus 로고
    • Partial order verification with PEP
    • Aug.
    • E. Best. Partial Order Verification with PEP. POMIV, Aug. 1996.
    • (1996) POMIV
    • Best, E.1
  • 31
    • 77957576399 scopus 로고    scopus 로고
    • Fast four-phase tree FIFO
    • Dec. University of Newcastle upon Tyne
    • A. Bystrov, A. Yakovlev. Fast Four-Phase Tree FIFO. 7th UK Asynchronous Forum, Dec. 1999, University of Newcastle upon Tyne.
    • (1999) 7th UK Asynchronous Forum
    • Bystrov, A.1    Yakovlev, A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.