Automated synthesis of micro-pipelines from behavioral Verilog HDL

Proceedings - International Symposium on Asynchronous Circuits and Systems

Volumn , Issue , 2000, Pages 84-92

  Blunno, Ivan ^a   Lavagno, Luciano ^b  

^a POLITECNICO DI TORINO   (Italy)

^b UNIVERSITY OF UDINE   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS CONTROL UNITS; ASYNCHRONOUS DESIGN; AUTOMATED SYNTHESIS; CONTROL UNIT; DATA PATHS; MICRO-PIPELINES; NETLIST; PHYSICAL DESIGN; SIGNAL TRANSITION GRAPHS; STANDARD CELL; STANDARD HARDWARE; SYNTHESIS TOOL; VERILOG; VERILOG HDL;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DESIGN; ELECTRIC BATTERIES; INTEGRATED CIRCUIT MANUFACTURE; PROGRAM COMPILERS; RESEARCH;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 77957960379     PISSN: 15228681     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.2000.836967     Document Type: Conference Paper

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