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Volumn 10, Issue , 2004, Pages 135-145

Synthesis of speed independent circuits based on decomposition

Author keywords

Abstraction; Decomposition; Speed independent circuits; STGs; Synthesis

Indexed keywords

ABSTRACTION; SPEED-INDEPENDENT CIRCUITS; STG;

EID: 2942657343     PISSN: 15228681     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Conference Paper
Times cited : (14)

References (22)
  • 3
    • 0003885785 scopus 로고    scopus 로고
    • Minimalist: An environment for the synthesis, verification and testability of burst-mode asynchronous ma chines
    • Columbia Uni versity, NY, July
    • R. M. Fuhrer, S. M. Nowick, M. Theobald, N. K. Jha, B. Lin, and L. Plana. Minimalist: An environment for the synthesis, verification and testability of burst-mode asynchronous ma chines. Technical Report TR CUCS-020-99, Columbia Uni versity, NY, July 1999.
    • (1999) Technical Report , vol.TR CUCS-020-99
    • Fuhrer, R.M.1    Nowick, S.M.2    Theobald, M.3    Jha, N.K.4    Lin, B.5    Plana, L.6
  • 4
    • 0005336517 scopus 로고
    • Syntax-directed trans lation of concurrent programs into self-timed circuits
    • J. Allen and F. Leighton, editors, MIT Press
    • Steven M. Burns and Alain J. Martin. Syntax-directed trans lation of concurrent programs into self-timed circuits. In J. Allen and F. Leighton, editors, Advanced Research in VLSI, pages 35-50. MIT Press, 1988.
    • (1988) Advanced Research in VLSI , pp. 35-50
    • Burns, S.M.1    Martin, A.J.2
  • 8
    • 0036173333 scopus 로고    scopus 로고
    • An asyn chronous hardware synthesis language
    • Doug Edwards and Andrew Bardsley. Balsa: An asyn chronous hardware synthesis language. The Computer Journal, 45(1):12-18, 2002.
    • (2002) The Computer Journal , vol.45 , Issue.1 , pp. 12-18
    • Edwards, D.1    Balsa, A.B.2
  • 10
    • 0036054368 scopus 로고    scopus 로고
    • Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems
    • June
    • Tiberiu Chelcea and Steven M. Nowick. Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems. In Proc. ACM/IEEE Design Automa tion Conference, June 2002.
    • (2002) Proc. ACM/IEEE Design Automa Tion Conference
    • Chelcea, T.1    Nowick, S.M.2
  • 11
    • 0027617937 scopus 로고
    • Synthesis of timed asynchronous circuits
    • June
    • Chris J. Myers and Teresa H.-Y. Meng. Synthesis of timed asynchronous circuits. IEEE Transactions on VLSI Systems, 1(2):106-119, June 1993.
    • (1993) IEEE Transactions on VLSI Systems , vol.1 , Issue.2 , pp. 106-119
    • Myers, C.J.1    Meng, T.H.-Y.2
  • 12
    • 0345272604 scopus 로고    scopus 로고
    • Synthesizing timed cir cuits from high level specification languages
    • Tomohiro Yoneda and Chris Myers. Synthesizing timed cir cuits from high level specification languages. NII Technical Report, NII-2003-003E, 2003.
    • (2003) NII Technical Report , vol.NII-2003-003E
    • Yoneda, T.1    Myers, C.2
  • 15
    • 2942695812 scopus 로고    scopus 로고
    • Decomposition in asyn chronous circuit design
    • J. Cortadella, A. Yakovlev, and G. Rozenberg, editors, Springer-Verlag
    • Walter Vogler and Ralf Wollowski. Decomposition in asyn chronous circuit design. In J. Cortadella, A. Yakovlev, and G. Rozenberg, editors, Concurrency and Hardware Design, volume 2549 of Lecture Notes in Computer Science, pages 152-190. Springer-Verlag, 2002.
    • (2002) Concurrency and Hardware Design, Volume 2549 of Lecture Notes in Computer Science , vol.2549 , pp. 152-190
    • Vogler, W.1    Wollowski, R.2
  • 17
    • 0028562785 scopus 로고
    • A modular partitioning approach for asynchronous circuit synthesis
    • June
    • Ruchir Pun and Jun Gu. A modular partitioning approach for asynchronous circuit synthesis. In Proc. ACM/IEEE Design Automation Conference, pages 63-69, June 1994.
    • (1994) Proc. ACM/IEEE Design Automation Conference , pp. 63-69
    • Pun, R.1    Gu, J.2
  • 20
    • 33847258494 scopus 로고
    • Using unfoldings to avoid the state ex plosion problem in the verification of asynchronous circuits
    • G. v. Bochman and D. K. Probst, editors, Springer-Verlag
    • Kenneth McMillan. Using unfoldings to avoid the state ex plosion problem in the verification of asynchronous circuits. In G. v. Bochman and D. K. Probst, editors, Proc. Inter national Workshop on Computer Aided Verification, volume 663 of Lecture Notes in Computer Science, pages 164-177. Springer-Verlag, 1992.
    • (1992) Proc. Inter National Workshop on Computer Aided Verification, Volume 663 of Lecture Notes in Computer Science , vol.663 , pp. 164-177
    • McMillan, K.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.