-
1
-
-
0032122009
-
Monolithic packaging concepts for high isolation in circuits and antennas
-
Jul
-
R. F. Drayton, R. M. Henderson, and L. P. B. Katehi, "Monolithic packaging concepts for high isolation in circuits and antennas," IEEE Trans. Microw. Theory Tech., vol. 46, no. 7, pp. 900-906, Jul. 1998.
-
(1998)
IEEE Trans. Microw. Theory Tech
, vol.46
, Issue.7
, pp. 900-906
-
-
Drayton, R.F.1
Henderson, R.M.2
Katehi, L.P.B.3
-
2
-
-
0030126721
-
Substrate crosstalk in BiCMOS mixed mode integrated circuits
-
Apr
-
K. Joardar, "Substrate crosstalk in BiCMOS mixed mode integrated circuits," Solid State Electron., vol. 39, no. 4, pp. 511-516, Apr. 1996.
-
(1996)
Solid State Electron
, vol.39
, Issue.4
, pp. 511-516
-
-
Joardar, K.1
-
3
-
-
0035696726
-
Improved latch-up immunity in junction-isolated smart power ICs with unbiased guard ring
-
Dec
-
S. Gupta, J. C. Beckman, and S. L. Kosier, "Improved latch-up immunity in junction-isolated smart power ICs with unbiased guard ring," IEEE Electron Device Lett., vol. 22, no. 12, pp. 600-602, Dec. 2001.
-
(2001)
IEEE Electron Device Lett
, vol.22
, Issue.12
, pp. 600-602
-
-
Gupta, S.1
Beckman, J.C.2
Kosier, S.L.3
-
4
-
-
33845873921
-
Coupling effects of dual SiGe power amplifier for 802.11n MIMO applications
-
Jun
-
W. C. Hua, P. T. Lin, C. P. Lin, C. Y. Lin, H. L. Chang, C. W. Liu, T. Y. Yang, and G. K. Ma, "Coupling effects of dual SiGe power amplifier for 802.11n MIMO applications," in Proc. IEEE Radio Freq. Integr. Circuits Symp. Dig., Jun. 2006, pp. 65-68.
-
(2006)
Proc. IEEE Radio Freq. Integr. Circuits Symp. Dig
, pp. 65-68
-
-
Hua, W.C.1
Lin, P.T.2
Lin, C.P.3
Lin, C.Y.4
Chang, H.L.5
Liu, C.W.6
Yang, T.Y.7
Ma, G.K.8
-
5
-
-
0031341419
-
Substrate crosstalk reduction using SOI technology
-
Dec
-
J. P. Raskin, A. Viviani, D. Flandre, and J. P. Colinge, "Substrate crosstalk reduction using SOI technology," IEEE Trans. Electron Devices, vol. 44, no. 12, pp. 2252-2261, Dec. 1997.
-
(1997)
IEEE Trans. Electron Devices
, vol.44
, Issue.12
, pp. 2252-2261
-
-
Raskin, J.P.1
Viviani, A.2
Flandre, D.3
Colinge, J.P.4
-
6
-
-
0000510384
-
A Faraday cage isolation structure for substrate crosstalk suppression
-
Oct
-
J. H. Wu, J. Scholvin, J. A. del Alamo, and K. A. Jenkins, "A Faraday cage isolation structure for substrate crosstalk suppression," IEEE Trans. Microw. Wireless Compon. Lett., vol. 11, no. 10, pp. 410-412, Oct. 2001.
-
(2001)
IEEE Trans. Microw. Wireless Compon. Lett
, vol.11
, Issue.10
, pp. 410-412
-
-
Wu, J.H.1
Scholvin, J.2
del Alamo, J.A.3
Jenkins, K.A.4
-
7
-
-
0036503255
-
+ Si substrates with semi-insulating porous Si
-
Mar
-
+ Si substrates with semi-insulating porous Si," IEEE Electron Device Lett., vol. 23, no. 3, pp. 160-162, Mar. 2002.
-
(2002)
IEEE Electron Device Lett
, vol.23
, Issue.3
, pp. 160-162
-
-
Kim, H.S.1
Jenkins, K.A.2
Xie, Y.H.3
-
8
-
-
27144442793
-
Low capacitance and high isolation bond pad for high frequency RFICs
-
Oct
-
K. Chong and Y. H. Xie, "Low capacitance and high isolation bond pad for high frequency RFICs," IEEE Electron Device Lett., vol. 26, no. 10, pp. 746-748, Oct. 2005.
-
(2005)
IEEE Electron Device Lett
, vol.26
, Issue.10
, pp. 746-748
-
-
Chong, K.1
Xie, Y.H.2
-
9
-
-
0141918454
-
The importance of distributed grounding in combination with porous Si trenches for the reduction of RF crosstalk through p-Si substrate
-
Aug
-
H. S. Kim, K. C. Chong, Y. H. Xie, and K. A. Jenkins, "The importance of distributed grounding in combination with porous Si trenches for the reduction of RF crosstalk through p-Si substrate," IEEE Electron Device Lett., vol. 24, no. 8, pp. 640-642, Aug. 2003.
-
(2003)
IEEE Electron Device Lett
, vol.24
, Issue.8
, pp. 640-642
-
-
Kim, H.S.1
Chong, K.C.2
Xie, Y.H.3
Jenkins, K.A.4
-
10
-
-
23844512679
-
+ Si substrate for mixed-signal system-on-chip (SoC)
-
Nov
-
+ Si substrate for mixed-signal system-on-chip (SoC)," IEEE Trans. Electron Devices, vol. 52, no. 11, pp. 2440-2446, Nov. 2005.
-
(2005)
IEEE Trans. Electron Devices
, vol.52
, Issue.11
, pp. 2440-2446
-
-
Chong, K.1
Zhang, X.2
Tu, K.N.3
Huang, D.4
Chang, M.C.5
Xie, Y.H.6
-
11
-
-
0036049043
-
A porous Si based novel isolation technology for mixed-signal integrated circuits
-
Jun
-
H. S. Kim, K. Chong, Y. H. Xie, M. Devincentis, T. Itoh, A. J. Becker, and K. A. Jenkins, "A porous Si based novel isolation technology for mixed-signal integrated circuits," in VLSI Symp. Technol. Dig., Jun. 2002, pp. 160-161.
-
(2002)
VLSI Symp. Technol. Dig
, pp. 160-161
-
-
Kim, H.S.1
Chong, K.2
Xie, Y.H.3
Devincentis, M.4
Itoh, T.5
Becker, A.J.6
Jenkins, K.A.7
-
12
-
-
34547778440
-
High- Q integrated inductor using post-CMOS selectively grown porous silicon (SGPS) technique for RFIC applications
-
Aug
-
C. Li, H. L. Liao, C. Wang, J. Yin, R. Huang, and Y. Y. Wang, "High- Q integrated inductor using post-CMOS selectively grown porous silicon (SGPS) technique for RFIC applications," IEEE Electron Device Lett., vol. 28, no. 8, pp. 763-766, Aug. 2007.
-
(2007)
IEEE Electron Device Lett
, vol.28
, Issue.8
, pp. 763-766
-
-
Li, C.1
Liao, H.L.2
Wang, C.3
Yin, J.4
Huang, R.5
Wang, Y.Y.6
-
13
-
-
0033726229
-
Porous silicon: A quantum sponge structure for silicon based optoelectronics
-
Apr
-
O. Bisi, S. Ossicini, and L. Pavesi, "Porous silicon: A quantum sponge structure for silicon based optoelectronics," Surf. Sci. Rep., vol. 38, no. 1, pp. 1-126, Apr. 2000.
-
(2000)
Surf. Sci. Rep
, vol.38
, Issue.1
, pp. 1-126
-
-
Bisi, O.1
Ossicini, S.2
Pavesi, L.3
-
14
-
-
0036836993
-
Formation and application of porous silicon
-
Nov
-
H. Foll, M. Christophersen, J. Carstensen, and G. Hasse, "Formation and application of porous silicon," Mater. Sci. Eng. Rev., vol. 39, no. 4, pp. 93-141, Nov. 2002.
-
(2002)
Mater. Sci. Eng. Rev
, vol.39
, Issue.4
, pp. 93-141
-
-
Foll, H.1
Christophersen, M.2
Carstensen, J.3
Hasse, G.4
-
15
-
-
34250783933
-
High-performance integrated inductor and effective crosstalk isolation using post-CMOS selective grown porous silicon technique for RFIC applications
-
Jun
-
C. Li, H. L. Liao, L. Yang, and R. Huang, "High-performance integrated inductor and effective crosstalk isolation using post-CMOS selective grown porous silicon technique for RFIC applications," Solid State Electron., vol. 51, no. 6, pp. 989-994, Jun. 2007.
-
(2007)
Solid State Electron
, vol.51
, Issue.6
, pp. 989-994
-
-
Li, C.1
Liao, H.L.2
Yang, L.3
Huang, R.4
-
16
-
-
0033875648
-
Physical modeling of spiral inductors on silicon
-
Mar
-
C. P. Yue and S. S. Wong, "Physical modeling of spiral inductors on silicon," IEEE Trans. Electron Devices, vol. 47, no. 3, pp. 560-568, Mar. 2000.
-
(2000)
IEEE Trans. Electron Devices
, vol.47
, Issue.3
, pp. 560-568
-
-
Yue, C.P.1
Wong, S.S.2
-
17
-
-
31044456941
-
Characteristic-function approach to parameter extraction for asymmetric equivalent circuit of on-chip spiral inductors
-
Jan
-
F. Y. Huang, N. Jiang, and E. Bian, "Characteristic-function approach to parameter extraction for asymmetric equivalent circuit of on-chip spiral inductors," IEEE Trans. Microw. Theory Tech., vol. 54, no. 1, pp. 115-119, Jan. 2006.
-
(2006)
IEEE Trans. Microw. Theory Tech
, vol.54
, Issue.1
, pp. 115-119
-
-
Huang, F.Y.1
Jiang, N.2
Bian, E.3
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