메뉴 건너뛰기




Volumn 26, Issue 10, 2005, Pages 746-748

Low capacitance and high isolation bond pad for high-frequency RFICs

Author keywords

Bond pad; Crosstalk; Parasitic capacitance; Porous Si (PS); Radio ferquency integrated circuit (RFIC)

Indexed keywords

ANODIC OXIDATION; CAPACITANCE; CMOS INTEGRATED CIRCUITS; CROSSTALK; CURRENT DENSITY; POROUS SILICON; REACTIVE ION ETCHING;

EID: 27144442793     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2005.854399     Document Type: Article
Times cited : (17)

References (15)
  • 1
    • 0035696650 scopus 로고    scopus 로고
    • "Design on the low-capacitance bond pad for high-frequency I/O circuits in CMOS"
    • Dec
    • M. D. Ker, H. C. Jiang, and C. Y. Chang, "Design on the low-capacitance bond pad for high-frequency I/O circuits in CMOS," IEEE Trans. Electron Device, vol. 48, no. 12, pp. 2953-2956, Dec. 2001.
    • (2001) IEEE Trans. Electron Device , vol.48 , Issue.12 , pp. 2953-2956
    • Ker, M.D.1    Jiang, H.C.2    Chang, C.Y.3
  • 2
    • 0036318817 scopus 로고    scopus 로고
    • "High-isolation bonding pad with depletion-insulation structure for RF/microwave integrated circuits on bulk silicon CMOS"
    • S. Lam, W. H. Ki, and M. Chan, "High-isolation bonding pad with depletion-insulation structure for RF/microwave integrated circuits on bulk silicon CMOS," in IEEE MTT-S Dig., 2002, pp. 677-680.
    • (2002) IEEE MTT-S Dig. , pp. 677-680
    • Lam, S.1    Ki, W.H.2    Chan, M.3
  • 4
    • 0000133648 scopus 로고    scopus 로고
    • "Effects of substrate resistances on LNA performance and a bondpad structure for reducing the effects in a silicon bipolar technology"
    • Sep. O K.K.
    • J. T. Colvin, S. S. Bhatia, and K. K. O, "Effects of substrate resistances on LNA performance and a bondpad structure for reducing the effects in a silicon bipolar technology," IEEE J. Solid-State Circuits, vol. 34, no. 9, pp. 1339-1334, Sep. 1999.
    • (1999) IEEE J. Solid-State Circuits , vol.34 , Issue.9 , pp. 1334-1339
    • Colvin, J.T.1    Bhatia, S.S.2
  • 6
    • 0141595168 scopus 로고    scopus 로고
    • "High-isolation bonding pad design for silicon RFIC up to 20 GHz"
    • Sep
    • S. Lam, P. K. T. Mok, P. K. Ko, and M. Chan, "High-isolation bonding pad design for silicon RFIC up to 20 GHz," IEEE Electron Device Lett., vol. 24, no. 9, pp. 601-603, Sep. 2003.
    • (2003) IEEE Electron Device Lett. , vol.24 , Issue.9 , pp. 601-603
    • Lam, S.1    Mok, P.K.T.2    Ko, P.K.3    Chan, M.4
  • 7
    • 36449005188 scopus 로고
    • "Atmospheric impregnation of porous silicon at room temperature"
    • Jul
    • L. T. Canham, M. R. Houlton, W. Y. Leong, C. Picketing, and J. M. Keen, "Atmospheric impregnation of porous silicon at room temperature," J. Appl. Phys., vol. 70, pp. 422-431, Jul. 1991.
    • (1991) J. Appl. Phys. , vol.70 , pp. 422-431
    • Canham, L.T.1    Houlton, M.R.2    Leong, W.Y.3    Picketing, C.4    Keen, J.M.5
  • 8
    • 0019663481 scopus 로고
    • "Full isolation technology by porous oxidized silicon and its application to LSIs"
    • K. Imai and S. Nakajima, "Full isolation technology by porous oxidized silicon and its application to LSIs," in IEDM Tech. Dig., 1981, pp. 376-379.
    • (1981) IEDM Tech. Dig. , pp. 376-379
    • Imai, K.1    Nakajima, S.2
  • 9
    • 23844512679 scopus 로고    scopus 로고
    • "Three-dimensional substrate impedance engineering based on p-/p+ Si substrate for mixed-signal system-on-chip (SoC)"
    • to be published
    • K. Chong, X. Zhang, K. N. Tu, D. Huang, M. C. F. Chang, and Y. H. Xie, "Three-dimensional substrate impedance engineering based on p-/p+ Si substrate for mixed-signal system-on-chip (SoC)," IEEE Trans. Electron Devices, to be published.
    • IEEE Trans. Electron Devices
    • Chong, K.1    Zhang, X.2    Tu, K.N.3    Huang, D.4    Chang, M.C.F.5    Xie, Y.H.6
  • 10
    • 13444292413 scopus 로고    scopus 로고
    • "High performance inductors integrated on porous silicon"
    • Feb
    • K. Chong, Y. H. Xie, K. W. Yu, D. Huang, and M. C. F. Chang, "High performance inductors integrated on porous silicon," IEEE Electron Device Lett., vol. 26, no. 2, pp. 93-95, Feb. 2005.
    • (2005) IEEE Electron Device Lett. , vol.26 , Issue.2 , pp. 93-95
    • Chong, K.1    Xie, Y.H.2    Yu, K.W.3    Huang, D.4    Chang, M.C.F.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.