Improved latch-up immunity in junction-isolated smart power ICs with unbiased guard ring

IEEE Electron Device Letters

Volumn 22, Issue 12, 2001, Pages 600-602

  Gupta, Sandhya ^a,b   Beckman, J C ^a,b   Kosier, S L ^a,b  

^a IEEE   (United States)

^b PolarFab   (United States)

Author keywords

Crosstalk; Crosstalk isolation; Current carrying capability; High voltage LDMOS; Isolation technology; Latch up; Latch up immunity; Low voltage CMOS control circuit; Power IC technology

Indexed keywords

CROSSTALK ISOLATION; GUARD RINGS;

CHARGE CARRIERS; CMOS INTEGRATED CIRCUITS; CROSSTALK; ELECTRIC CURRENTS; GAIN MEASUREMENT; SEMICONDUCTOR JUNCTIONS;

POWER INTEGRATED CIRCUITS;

EID: 0035696726     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.974591     Document Type: Article

References (7)

1. Power mosfets driving circuits and protection techniques
2. A power IC technology with excellent cross-talk isolation
3. Latchup in CMOS technology
4. DC substrate coupling between LDMOS and CMOS devices in hyperintegration I technology
5. Reverse channel floating base emitter switched thyristor (RFB-EST)
6. Smart power approaches VLSI complexity
7. Multi-ring active analogic protection for minority carrier injection suppression in smart power technology