Three-dimensional substrate impedance engineering based on p-/p+ Si substrate for mixed-signal system-on-chip (SoC)

IEEE Transactions on Electron Devices

Volumn 52, Issue 11, 2005, Pages 2440-2446

  Chong, Kyuchul ^a   Zhang, Xi ^a   Tu, King Ning ^a   Huang, Daquan ^a   Chang, Mau Chung ^a   Xie, Ya Hong ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Crosstalk; Mixed signal system on chip (SoC); On chip inductor; Porous Si; Radio frequency (RF) isolation

Indexed keywords

CMOS INTEGRATED CIRCUITS; CROSSTALK; ELECTRIC IMPEDANCE; ELECTRIC INDUCTORS; ELECTROLESS PLATING; FARADAY EFFECT; NATURAL FREQUENCIES; POROUS SILICON; Q FACTOR MEASUREMENT; SEMICONDUCTING SILICON; SUBSTRATES;

MIXED-SIGNAL SYSTEM-ON-CHIP (SOC); ON-CHIP INDUCTOR; RADIO FREQUENCY (RF) ISOLATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 23844512679     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.857190     Document Type: Article

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