-
1
-
-
84889831892
-
Exploring Potential Benefits of 3D FPGA Integration
-
Springer Berlin /Heidelberg
-
C. Ababei, P. Maidee, and K. Bazargan, "Exploring Potential Benefits of 3D FPGA Integration," in Field Programmable Logic and Application, vol. 3203/2004: Springer Berlin /Heidelberg, 2004.
-
(2004)
Field Programmable Logic and Application
, vol.3203
-
-
Ababei, C.1
Maidee, P.2
Bazargan, K.3
-
2
-
-
2142660781
-
The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density
-
March
-
E. Ahmed and J. Rose, "The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density," in IEEE Trans. on VLSI, Vol 12, No. 3, pp. 288-298, March 2004.
-
(2004)
IEEE Trans. on VLSI
, vol.12
, Issue.3
, pp. 288-298
-
-
Ahmed, E.1
Rose, J.2
-
3
-
-
3242676271
-
Fabrication of 5 nm linewidth and 14 nm pitch features by nanoimprint lithography
-
M. D. Austin, A. Ge, W. Wu, M. Li, Z. Yu, et al., "Fabrication of 5 nm linewidth and 14 nm pitch features by nanoimprint lithography," App. Phy. Lett, vol. 84, no. 26, pp. 5299-5301, 2004.
-
(2004)
App. Phy. Lett
, vol.84
, Issue.26
, pp. 5299-5301
-
-
Austin, M.D.1
Ge, A.2
Wu, W.3
Li, M.4
Yu, Z.5
-
5
-
-
16244418071
-
DAOmap: A Depth-Optimal Area Optimization Mapping Algorithm for FPGA Designs
-
Nov
-
D. Chen and J. Cong, "DAOmap: A Depth-Optimal Area Optimization Mapping Algorithm for FPGA Designs," ICCAD, Nov. 2004.
-
(2004)
ICCAD
-
-
Chen, D.1
Cong, J.2
-
6
-
-
0037392525
-
Nanoscale molecular-switch crossbar circuits
-
Y. Chen, G.-Y. Jung, D. A. A. Ohlberg, X. Li, et al., "Nanoscale molecular-switch crossbar circuits," Nanotechnology, vol. 14, 2003.
-
(2003)
Nanotechnology
, vol.14
-
-
Chen, Y.1
Jung, G.-Y.2
Ohlberg, D.A.A.3
Li, X.4
-
7
-
-
28344452134
-
Demystifying 3D ICs: The pros and cons of going vertical
-
W. R. Davis, et al., "Demystifying 3D ICs: the pros and cons of going vertical," IEEE, Design & Test of Computers, vol. 22, no. 6, pp. 498-510, 2005.
-
(2005)
IEEE, Design & Test of Computers
, vol.22
, Issue.6
, pp. 498-510
-
-
Davis, W.R.1
-
8
-
-
85015357431
-
Nanowire-based programmable architectures
-
A. DeHon, "Nanowire-based programmable architectures," ACM Journal on Emerging Technologies in Computing Systems, vol. 1, no. 2, pp. 109-162, 2005.
-
(2005)
ACM Journal on Emerging Technologies in Computing Systems
, vol.1
, Issue.2
, pp. 109-162
-
-
DeHon, A.1
-
10
-
-
50349091296
-
Exploring Carbon Nanotubes and NiSi Nanowires As On-Chip Interconnections
-
C. Dong and W. Wang, "Exploring Carbon Nanotubes and NiSi Nanowires As On-Chip Interconnections" ISCAS 2006.
-
(2006)
ISCAS
-
-
Dong, C.1
Wang, W.2
-
11
-
-
27944496952
-
-
A. Gayasen, N. Vijaykrishana, M. J. Irwin, Exploring Technology Alternatives for Nano-Scale FPGA Interconnects, DAC, 2005.
-
A. Gayasen, N. Vijaykrishana, M. J. Irwin, "Exploring Technology Alternatives for Nano-Scale FPGA Interconnects", DAC, 2005.
-
-
-
-
13
-
-
0000636881
-
Electrical and Thermal Transport Properties of Magnetically Aligned Single Wall Carbon Nanotube Films
-
J. Hone, et al, "Electrical and Thermal Transport Properties of Magnetically Aligned Single Wall Carbon Nanotube Films," App. Phy. Lett., vol. 77, No. 5, pp. 666-668, 2000.
-
(2000)
App. Phy. Lett
, vol.77
, Issue.5
, pp. 666-668
-
-
Hone, J.1
-
14
-
-
8644228615
-
Carbon nanotube vias for future LSI interconnects
-
June
-
A. Kawabata, et.al. "Carbon nanotube vias for future LSI interconnects", IEEE Inter. Interconnect Tech. Conf., June 2004.
-
(2004)
IEEE Inter. Interconnect Tech. Conf
-
-
Kawabata, A.1
-
15
-
-
27744497504
-
-
F. Li, Y. Lin, L. He, D. Chen, and J. Cong, Power Modeling and Characteristics of Field Programmable Gate Arrays, TCAD, 24, Issue 11, pp. 1712-1724, Nov. 2005.
-
F. Li, Y. Lin, L. He, D. Chen, and J. Cong, "Power Modeling and Characteristics of Field Programmable Gate Arrays," TCAD, vol. 24, Issue 11, pp. 1712-1724, Nov. 2005.
-
-
-
-
16
-
-
33745817849
-
Performance Benefits of Monolithically Stacked 3D-FPGA
-
M. Lin, A. El Gamal, Y.C. Lu, S. Wong, "Performance Benefits of Monolithically Stacked 3D-FPGA," FPGA, 2006.
-
(2006)
FPGA
-
-
Lin, M.1
El Gamal, A.2
Lu, Y.C.3
Wong, S.4
-
17
-
-
13444256520
-
Performance comparison between carbon nanotube and copper interconnects for gigascale integration (GSI)
-
Feb
-
A. Naeemi, R. Sarvari, and J. D. Meindl, "Performance comparison between carbon nanotube and copper interconnects for gigascale integration (GSI)", IEEE Electron Device Letters, vol. 26, pp. 84-86, Feb. 2005.
-
(2005)
IEEE Electron Device Letters
, vol.26
, pp. 84-86
-
-
Naeemi, A.1
Sarvari, R.2
Meindl, J.D.3
-
18
-
-
34547144377
-
A New Hybrid FPGA with Nanoscale Clusters and CMOS Routing
-
R. M. P. Rad and M. Tehranipoor, "A New Hybrid FPGA with Nanoscale Clusters and CMOS Routing," in DAC 2006.
-
(2006)
DAC
-
-
Rad, R.M.P.1
Tehranipoor, M.2
-
19
-
-
21844468998
-
Circuit Modeling of Carbon Nanotube Interconnects and their Performance Estimation in VLSI Design
-
West Lafayette, Nov
-
A. Raychowdhury and K. Roy, "Circuit Modeling of Carbon Nanotube Interconnects and their Performance Estimation in VLSI Design", Proc. of IWCE, West Lafayette, Nov 2004.
-
(2004)
Proc. of IWCE
-
-
Raychowdhury, A.1
Roy, K.2
-
20
-
-
31344449874
-
Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technology
-
Jan
-
A. Raychowdhury and K. Roy, "Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technology," TCAD, vol. 25, no. 1, Jan. 2006.
-
(2006)
TCAD
, vol.25
, Issue.1
-
-
Raychowdhury, A.1
Roy, K.2
-
21
-
-
0003934798
-
-
Dept. of Electrical Engineering and Computer Science, University of California, Berkeley, CA 94720
-
E. M. Sentovich et. al. "SIS: A System for Sequential Circuit Synthesis," Dept. of Electrical Engineering and Computer Science, University of California, Berkeley, CA 94720, 1992.
-
(1992)
SIS: A System for Sequential Circuit Synthesis
-
-
Sentovich, E.M.1
et., al.2
-
22
-
-
33846807711
-
Nano/CMOS architecture using a field-programmable nanowire interconnect
-
G. Snider and S. Williams, "Nano/CMOS architecture using a field-programmable nanowire interconnect," Nanotechnology, vol. 18, 2007.
-
(2007)
Nanotechnology
, vol.18
-
-
Snider, G.1
Williams, S.2
-
23
-
-
4344644019
-
CMOS-like logic in defective nanoscale crossbars
-
G. Snider, P. Kuekes, and R. S. Williams, "CMOS-like logic in defective nanoscale crossbars," Nanotechnology, vol. 15, 2004.
-
(2004)
Nanotechnology
, vol.15
-
-
Snider, G.1
Kuekes, P.2
Williams, R.S.3
-
24
-
-
33750340818
-
Carbon nanotube interconnects: Implications for performance, power dissipation and thermal management
-
N. Srivastava, R. V. Joshi, and K. Banerjee, "Carbon nanotube interconnects: implications for performance, power dissipation and thermal management," IEDM, pp. 249-252, 2005.
-
(2005)
IEDM
, pp. 249-252
-
-
Srivastava, N.1
Joshi, R.V.2
Banerjee, K.3
-
25
-
-
18744373862
-
CMOL FPGA: A reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices
-
D. B. Sfrukov and K. K. Likharev, "CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices," Nanotechnology, vol. 16, no. 888-900, 2005.
-
(2005)
Nanotechnology
, vol.16
, Issue.888-900
-
-
Sfrukov, D.B.1
Likharev, K.K.2
-
26
-
-
3142684485
-
Single-crystal metallic nanowires and metal/semiconductor nanowire heterostructures
-
July
-
Y. Wu, J. Xiang, C. Yang, W. Lu, and C. M. Lieber, "Single-crystal metallic nanowires and metal/semiconductor nanowire heterostructures", Nature, vol. 430, pp. 61-65, July 2004.
-
(2004)
Nature
, vol.430
, pp. 61-65
-
-
Wu, Y.1
Xiang, J.2
Yang, C.3
Lu, W.4
Lieber, C.M.5
-
27
-
-
85165842645
-
-
W. Zhang, N. Jha, and L. Shang, NATURE: A Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture, DAC, 2006.
-
W. Zhang, N. Jha, and L. Shang, "NATURE: A Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture," DAC, 2006.
-
-
-
-
28
-
-
50349100954
-
-
"International technology roadmap for semiconductors," http://public.itrs.net, 2005.
-
(2005)
-
-
-
29
-
-
50349099652
-
-
NRAM™
-
NRAM™, Nantero, http://www.nantero.com/tech.html.
-
Nantero
-
-
|