On-chip thermal gradient analysis and temperature flattening for SoC design

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E88-A, Issue 12, 2005, Pages 3382-3388

  Sato, Takashi ^a,f   Ichimiya, Junji ^b,e   Ono, Nobuto ^c,g   Hachiya, Koutaro ^a,f,h,i,j   Hashimoto, Masanori ^d  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b RICOH COMPANY LTD   (Japan)

^c JEDAT Incorporated   (Japan)

^d OSAKA UNIVERSITY   (Japan)

^e FUJITSU LABORATORIES LTD   (Japan)

^f IEEE   (Japan)

^g Jedat Innovation Inc   (Japan)

^h IPSJ   (Japan)

ⁱ IIEEJ

^j Jedat Innovation Inc ^*

more..

Author keywords

Clock skew; Reliability; Temperature flattening; Thermal gradient; Thermal simulation; Timing

Indexed keywords

COMPUTER SIMULATION; MICROPROCESSOR CHIPS; RELIABILITY; SENSITIVITY ANALYSIS; STORAGE ALLOCATION (COMPUTER); THERMAL EFFECTS; THERMAL GRADIENTS;

FLOORPLAN MODIFICATION; POWER DENSITY; TEMPERATURE DIFFERENCE; THERMAL SIMULATION;

THERMOANALYSIS;

EID: 29144494605     PISSN: 09168508     EISSN: 17451337     Source Type: Journal    
DOI: 10.1093/ietfec/e88-a.12.3382     Document Type: Article

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