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Volumn 54, Issue 10, 2008, Pages 929-934

An efficient architecture for designing reverse converters based on a general three-moduli set

Author keywords

Computer arithmetic; New chinese remainder theorem 1 (New CRT I); Residue number system (RNS); Residue to binary converter; Reverse converter

Indexed keywords

COMPUTER ARITHMETIC; EFFICIENT ARCHITECTURE; HIGH SPEEDS; NEW CHINESE REMAINDER THEOREM 1 (NEW CRT-I); RESIDUE NUMBER SYSTEM (RNS); RESIDUE TO BINARY CONVERTER; REVERSE CONVERTER; REVERSE CONVERTERS; THREE-MODULI SET;

EID: 49749114851     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2008.03.006     Document Type: Article
Times cited : (24)

References (22)
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    • Hosseinzadeh, M.1    Navi, K.2
  • 6
    • 0033905449 scopus 로고    scopus 로고
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    • Wang Y. Residue-to-binary converters based on new Chinese remainder theorems. IEEE Transactions on Circuits and Systems II 47 3 (2000) 197-205
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  • 8
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    • Jenkins, W.K.1    Leon, B.J.2
  • 15
    • 13144269640 scopus 로고    scopus 로고
    • VLSI implementation of new arithmetic residue to binary decoders
    • Hiasat A.A. VLSI implementation of new arithmetic residue to binary decoders. IEEE Transactions on VLSI Systems 13 1 (2005) 153-158
    • (2005) IEEE Transactions on VLSI Systems , vol.13 , Issue.1 , pp. 153-158
    • Hiasat, A.A.1
  • 18
    • 0024072353 scopus 로고
    • Fast conversion between binary and residue numbers
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    • Guan, B.1    Jones, E.V.2
  • 19
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    • Design of residue generators and multioperand modular adders using carry-save adders
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    • Piestrak, S.J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.