High-speed parallel-prefix modulo 2n - 1 adders

IEEE Transactions on Computers

Volumn 49, Issue 7, 2000, Pages 673-680

  Kalampoukas, Lampros ^a,b   Nikolos, Dimitris ^a,c   Efstathiou, Costas ^d   Vergos, Haridimos T ^c   Kalamatianos, John ^a,e  

^a IEEE   (United States)

^b Xebeo Communications Inc   (United States)

^c UNIVERSITY OF PATRAS   (Greece)

^d UNIVERSITY OF WEST ATTICA   (Greece)

^e Northeastern University   (United States)

Author keywords

Carry look ahead adders; Parallel prefix adders; VLSI design

Indexed keywords

CARRY LOGIC; CMOS INTEGRATED CIRCUITS; LOGIC GATES; PARALLEL PROCESSING SYSTEMS; THEOREM PROVING; VLSI CIRCUITS;

CARRY LOOKAHEAD ADDERS; MODULO; PARALLEL PREFIX ADDERS;

ADDERS;

EID: 0034215841     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.863036     Document Type: Article

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