A study of the residue-to-binary converters for the three-moduli sets

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 50, Issue 2, 2003, Pages 235-243

  Wang, Wei ^a   Swamy, M N S ^b   Ahmad, M Omair ^b   Wang, Yuke ^c  

^a UNIVERSITY OF WESTERN ONTARIO   (Canada)

^b Dept of Electrical and Computer Engineering   (Canada)

^c The University of Texas at Dallas   (United States)

Author keywords

Chinese remainder theorem (CRT); Residue number system (RNS); Residue to binary (R B) converter; Three moduli sets; VLSI implementation

Indexed keywords

ALGORITHMS; BINARY SEQUENCES; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; INTEGRATED CIRCUIT LAYOUT; NUMBER THEORY; SET THEORY; VLSI CIRCUITS;

CHINESE REMAINDER THEOREM; RESIDUE NUMBER SYSTEM; RESIDUE-TO-BINARY CONVERTER;

DIGITAL ARITHMETIC;

EID: 0037301573     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2002.808191     Document Type: Article

References (26)

1. H. L. Garner, "The residue number system," IRE Trans. Electro. Comput., vol. EC-8, pp. 140-147, June 1959.
2. M. A. Soderstrand, Residue Number System Arithmetic: Modern Applications in Digital Signal Processing. New York: IEEE Press, 1986.
3. N. Szabo and R. Tanaka, Residue Arithmetic and Its Applications to Computer Technology. New York: McGraw-Hill, 1967.
4. Koren, Computer Arithmetic Algorithms. Englewood Cliffs, NJ: Prentice-Hall, 1993.
5. G. C. Cardarilli, M. Er, and R. Lojacona, "RNS-to-binary conversion for efficient VLSI implementation," IEEE Trans. Circuits Syst. II, vol. 45, pp. 667-669, June 1998.
6. W. K. Jenkins and B. J. Leon, "The use of residue number systems in the design of finite impulse response digital filters," IEEE Trans. Circuits Syst., vol. CAS-24, pp. 191-201, Apr. 1977.
7. K. M. Ibrahim and S. N. Saloum, "An efficient residue to binary converter design," IEEE Trans. Circuits Syst., vol. 35, pp. 1156-1158, Sept. 1988.
8. S. J. Piestrak, "A high-speed realization of a residue to binary number system converter," IEEE Trans. Circuits Syst. II, vol. 42, pp. 661-663, Oct. 1995.
9. S. Andraos and H. Ahmad, "A new efficient memoryless residue to binary converter," IEEE Trans. Circuits Syst., vol. 35, pp. 1441-1444, Nov. 1988.
10. n + 1}," IEEE Trans. Circuits Syst. II, vol. 44, pp. 53-57, Jan. 1997.
11. B. Premkumar, "An RNS to binary converter in 2n + 1, 2n, 2n - 1 moduli set," IEEE Trans. Circuits Syst. II, vol. 39, pp. 480-482, July 1992.
12. ____, "An RNS to binary converter in a three moduli set with common factors," IEEE Trans. Circuits Syst. II, vol. 42, pp. 298-301, Apr. 1995.
13. k-1 - 1)," IEEE Trans. Circuits Syst., vol. 45, pp. 204-208, Feb. 1998.
14. F. Pourbigharaz and H. M. Yassine, "A signed-digit architecture for residue to binary transformation," IEEE Trans. Comput., vol. 46, pp. 1146-1150, Oct. 1997.
15. W. Wang, M. N. S. Swamy, M. O. Ahmad, and Y. Wang, "A parallel residue-to-binary converter," in Proc. IEEE Inte. Conf. Acoustics, Speech, and Signal Processing, Phoenix, AZ, Mar. 1999.
16. Y. Wang, "New Chinese remainder theorems," in Proc. 32nd Asilomar Conf. Signals, Systems and Computers, vol. 1, 1998, pp. 165-171.
17. ____, "Residue-to-binary converters based on new Chinese remainder theorems," IEEE Trans. Circuits Syst. II, vol. 47, pp. 197-205, Mar. 2000.
18. W. Wang, M. N. S. Swamy, M. O. Ahmad, and Y. Wang, "Applications of the new Chinese remainder theorems for three-moduli sets," in Proc. IEEE Canadian Conf. Electrical and Computer Engineering, vol. 1, Edmonton, Canada, May 1999, pp. 571-576.
19. P. V. A. Mohan, "Evaluation of fast conversion techniques for binary-residue number systems," IEEE Trans. Circuits Syst. I, vol. 45, pp. 754-757, Oct. 1998.
20. Y. Wang, X. Song, and M. Aboulhamid, "Near-optimal residue to binary converter for the moduli," in Proc. 8th Great Lakes Symp. VLSI, Feb. 1998.
21. Y. Wang, M. N. S. Swamy, and M. O. Ahmad, "Residue-to-binary converters for three moduli sets," IEEE Trans. Circuits Syst. II, vol. 46, pp. 180-183, Feb. 1999.
22. W. Wang, M. N. S. Swamy, M. O. Ahmad, and Y. Wang, "A high-speed residue-to-binary converter and a scheme of its VLSI implementation," IEEE Trans. Circuits Syst. II, vol. 47, pp. 1576-1581, Dec. 2000.
23. S. Piestrak, "Design of residue generators and multioperand modular adders using carry-save adders," IEEE Trans. Comput., vol. 43, pp. 68-77, Jan. 1994.
24. k - 1 adder design," IEEE Trans. Circuits Syst. II, vol. 41, pp. 463-466, July 1994.
25. Canadian Microelectronics Corporation, Basic Digital IC Design Flow Instruction. Cambridge, U.K.: Kingston, Nov. 1997.
26. SYNOPSYS Reference Manual 3.0. Mountain View, CA: SYNOPSYS 1992.