VLSI implementation of new arithmetic residue to binary decoders

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 1, 2005, Pages 153-158

  Hiasat, Ahmad A ^a  

^a PRINCESS SUMAYA UNIVERSITY FOR TECHNOLOGY   (Jordan)

Author keywords

Arithmetic decoders; Binary number system; Converters; Residue number system

Indexed keywords

ALGORITHMS; COMPUTATIONAL METHODS; DIGITAL SIGNAL PROCESSING; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; ROM; VLSI CIRCUITS;

ARITHMETIC DECODERS; BINARY NUMBER SYSTEMS; CONVERTERS; RESIDUE NUMBER SYSTEM;

BINARY CODES;

EID: 13144269640     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.840400     Document Type: Article

References (15)

1. N. Szabo and R. Tanaka, Residue Arithmetic and Its Applications to Computer Technology. New York: McGraw Hill, 1967.
2. k-1 - 1)," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, pp. 204-209, Feb. 1998.
3. k-1 - 1)," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, pp. 1576-1581, Dec. 2000.
4. R. Conway and J. Nelson, "Fast converter for 3 moduli RNS using new property of CRT," IEEE Trans. Comput., vol. 48, pp. 852-860, Aug. 1999.
5. T. Van Vu, "Efficient implementations of Chinese remainder theorem for sign detection and residue decoding," IEEE Trans. Comput., vol. 34, pp. 646-651, Jul. 1985.
6. F. Pourbigharaz and H. Yassine, "A signed-digit architecture for residue to binary transformation," IEEE Trans. Comput., vol.46, pp. 1146-1150, Oct. 1997.
7. Y. Wang, "Residue-to-binary converters based on new Chinese remainder theorems," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, pp. 197-205, Mar. 2000.
8. A. Skavantzos, "An efficient residue to weighted converter for a new residue number system," in Proc. 8th Great Lakes Symp. on VLSI, Lafayette, LA, Feb. 1998, pp. 185-191.
9. 2n + 1} based on new Chinese remainder theorem," IEEE Trans. Circuits Syst. I, vol. 50, pp. 1296-1303, Oct. 2003.
10. A. Hiasat, "Efficient residue to binary converter," Proc. IEE Computers and Digital Techniques, vol. 150, pp. 11-16, Jan. 2003.
11. n - 1 adders," IEEE Trans. Comput., vol. 49, pp. 673-680, July 2000.
12. A. Hiasat, "New efficient structure for a modular multiplier for RNS," IEEE Trans. Comput., vol. 49, pp. 170-174. Feb. 2000.
13. Powerview [Online]. Available: http://www.viewlogic.com
14. R. W. Brodersen, Anatomy of Silicon Compiler. Norwell, MA: Kluwer, 1992.
15. A. Salz and M. Horowitz, "IRSIM: An incermental MOS switch-level simulator," in Proc. 26th Annu. ACM/IEEE Automation Conf., 1989, pp. 173-178.