An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures

Journal of Supercomputing

Volumn 45, Issue 3, 2008, Pages 341-364

  Flores, Antonio ^a   Aragón, Juan L ^a   Acacio, Manuel E ^a  

^a 30071 Campus de Espinardo   (Spain)

Author keywords

Chip multiprocessor; Heterogeneus on chip interconnection network; Microarchitectural level simulator; Parallel scientific applications; Power dissipation model

Indexed keywords

ENERGY EFFICIENCY; ENERGY POLICY; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; NANOTECHNOLOGY; STATIC ANALYSIS; TELECOMMUNICATION SYSTEMS; WIRE;

CHIP MULTI-PROCESSORS; CHIP-MULTIPROCESSOR; CLOCK FREQUENCIES; CMP ARCHITECTURES; CONTINUOUS IMPROVEMENTS; CRITICAL DESIGN; ENERGY CHARACTERISTICS; ENERGY CONSUMPTION; EXECUTION TIME; HETEROGENEUS ON-CHIP INTERCONNECTION NETWORK; MICRO-ARCHITECTURES; MICROARCHITECTURAL LEVEL SIMULATOR; ON-CHIP INTERCONNECTION NETWORKS; ON-CHIP WIRES; PARALLEL SCIENTIFIC APPLICATIONS; POWER CHARACTERISTICS; POWER DISSIPATION MODEL; POWER DISSIPATIONS; POWER-PERFORMANCE; PRECISE ANALYSIS; PROCESSOR CORES; SCIENTIFIC APPLICATIONS; SINGLE CHIPS; SYSTEM PERFORMANCES; TILED CMP; TOTAL ENERGIES;

ARCHITECTURAL DESIGN;

EID: 49149109434     PISSN: 09208542     EISSN: 15730484     Source Type: Journal    
DOI: 10.1007/s11227-008-0178-0     Document Type: Article

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