Disjoint pattern enumeration for custom instructions identification

Proceedings - 2007 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2007, Pages 273-278

  Yu, Pan ^a   Mitra, Tulika ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

ASIPs; Custom instruction; Customizable processors; Instruction set extensions; Subgraph enumeration algorithm

Indexed keywords

ASIPS; CUSTOM INSTRUCTION; CUSTOMIZABLE PROCESSORS; INSTRUCTION-SET EXTENSIONS; SUBGRAPH ENUMERATION ALGORITHM;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; APPLICATIONS; COMPUTER ARCHITECTURE; HEURISTIC METHODS; PROGRAM COMPILERS; PROGRAM PROCESSORS;

DATA FLOW ANALYSIS;

EID: 48149106346     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2007.4380659     Document Type: Conference Paper

References (25)

1. A. Aho, J. Hopcroft, and J.D. Ullman. Data structures and Algorithms. Addison-Wesley, 1987.
2. Altera. Nios embedded processor system development. http://www.altera. com/products/ip/processors/nios.
3. J. M. Arnold. S5: The architecture and development flow of a software configurable processor. In Proceedings of International Conference on Field-Programmable Technology (FPT), 2005.
4. M. Arnold and H. Corporaal. Designing domain-specific processors. In Proceedings of the Ninth International Symposium on Hardware/Software Codesign (CODES), 2001.
5. K. Atasu, D. G̈unhan, and and Özturan, Can. An integer linear programming approach for identifying instruction-set extensions. In CODES+ISSS, 2005
6. K. Atasu, L. Pozzi, and P. Ienne. Automatic application-specific instruction-set extensions under microarchitectural constraints. In Proceedings of the 40th Design Automation Conference (DAC), 2003.
7. M. Baleani et al. Hw/Sw partitioning and code generation of embedded control applications on a reconfigurable architecture platform. In CODES, May 2002.
8. P. Brisk, A. Kaplan, R. Kastner, and M. Sarrafzadeh. Instruction generation and regularity extraction for reconfigurable processors. In Proceedings of International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), October 2002.
9. D. Burger, T. Austin, and S. Bennett. Evaluating Future Microprocessors: The SimpleScalar Toolset. Technical Report CS-TR96-1308, Univ. of Wisconsin Madison, 1996. Available from http://www.simplescalar.com.
10. N. Clark, H. Zhong, and S. Mahlke. Processor acceleration through automated instruction set customization. In MICRO36, 2003.
11. J. Cong, Y. Fan, G. Han, and Z. Zhang. Application-specific instruction generation for configurable processor architectures. In FPGA, 2004.
12. P. Faraboschi et al. Lx: A technology platform for customizable VLIW embedded processing. In Proceedings of International Symposium on Computer Architecture (ISCA), 2000.
13. R. E. Gonzalez. Xtensa: A configurable and extensible processor. IEEE Micro, 20(2), 2000.
14. C. Galuzzi et al. Automatic selection of application-specific instruction-set extensions. In CODES+ISSS, 2006
15. M. R. Guthausch et al. Mibench: A free, commercially representative embedded benchmark suite. In IEEE 4th Annual Workshop on Workload Characterization, 2001. Benchmark available from http://www.eecs.umich.edu/ mibench/.
16. J. Lee, K. Choi, and N. Dutt. Efficient instruction encoding for automatic instruction set design of configurable ASIPs. In Proceedings of International Conference on Computer Aided Design (ICCAD), 2002.
17. R. Leupers and K. Karuri and S. Kraemer and M. Pandey. A design flow for configurable embedded processors based on optimized instruction set extension synthesis. In DATE, 2006
18. L. Pozzi, K. Atasu, and P. Ienne. Exact and Approximate Algorithms for the Extension of Embedded Processor Instruction Sets. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(7): 1209-29, July 2006.
19. L. Pozzi, M. Vuletic, and P. Ienne Automatic topology-based identification of instruction-set extensions for embedded processor. Technical Report 01/377, EPFL, 2001.
20. S. Talla. Adaptive Explicitly Parallel Instruction Computing. PhD thesis, New York University, 2000.
21. Xilinx Inc. Microblaze soft processor core.
22. P. Yu and T. Mitra. Characterizing embedded applications for instruction-set extensible processors. In DAC, 2004.
23. P. Yu and T. Mitra. Scalable custom instructions identification for instruction-set extensible processors. In CASES, 2004
24. P. Yu and T. Mitra. Efficient Custom Instruction Identification with Exact Enumeration. Technical Report TRB5/07, National University of Singapore, 2007
25. Z. A. Ye, A. Moshovos, S. Hauck, and P. Banerjee. Chimaera: A high-performance architecture with a tightly-coupled reconfigurable functional unit. In ISCA, 2000.