Implementing signatures for transactional memory

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2007, Pages 123-133

  Sanchez, Daniel ^a   Yen, Luke ^a   Hill, Mark D ^a   Sankaralingam, Karthikeyan ^a  

^a University of Wisconsin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BLOOMS (METAL); FUNCTIONS; STATIC RANDOM ACCESS STORAGE; STORAGE ALLOCATION (COMPUTER); WAVE FILTERS;

BLOOM FILTERING; CONCURRENT TRANSACTIONS; FALSE POSITIVE (FP); FORMAL ANALYSIS; HASH FUNCTIONS; HIGH QUALITY (HQ); INTERNATIONAL SYMPOSIUM; MICRO ARCHITECTURES; PERFORMANCE COSTS; SET INTERSECTION; SIMULATION-BASED; TRANSACTIONAL MEMORY (TM);

SET THEORY;

EID: 47349104267     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2007.24     Document Type: Conference Paper

References (33)

1. A. R. Alameldeen and D. A. Wood. Variability in architectural simulations of multi-threaded workloads. In Proc. of the 9th International Symposium on High-Performance Computer Architecture, Feb. 2003.
2. B. H. Bloom. Space/time trade-offs in hash coding with allowable errors. Commun. ACM, 13(7):422-426, July 1970.
3. F. Bonomi, M. Mitzenmacher, R. Panigrahy, S. Singh, and G. Varghese. An improved construction for counting Bloom filters. In Proc. of the European Symposium on Algorithms '06, pages 684-695, 2006.
4. A. Broder and M. Mitzenmacher. Network applications of Bloom filters: A survey. Internet Mathematics, 1(4):485-509, 2004.
5. J. L. Carter and M. N. Wegman. Universal classes of hash functions (Extended Abstract). In Proc. of the 9th Annual ACM Symposium on Theory of Computing, pages 106-112, 1977.
6. L. Carter, R. Floyd, J. Gill, G. Markowsky, and M. Wegman. Exact and approximate membership testers. In Proceedings of the 10th Annual ACM Symposium on Theory of Computing, pages 59-65, 1978.
7. L. Ceze, J. Tuck, C. Cascaval, and J. Torrellas. Bulk disambiguation of speculative threads in multiprocessors. In Proc. of the 33rd Annual International Symposium on Computer Architecture, June 2006.
8. L. Ceze, J. Tuck, P. Montesinos, and J. Torrellas. BulkSC: Bulk enforcement of sequential consistency. In Proc. of the 34th Annual International Symposium on Computer Architecture, June 2007.
9. S. Dharmapurikar, P. Krishnamurthy, T. Sproull, and J. Lockwood. Deep packet inspection using parallel Bloom filters. In Proc. of the Symposium on High Performance Interconnects '03, pages 44-51, Aug 2003.
10. L. Fan, P. Cao, J. Almeida, and A. Z. Broder. Summary cache: a scalable wide-area web cache sharing protocol. IEEE/ACM Trans. Netw., 8(3):281-293, 2000.
11. M. Ghosh, E. ? Ozer, S. Biles, and H.-H. S. Lee. Efficient System-on-Chip energymanagement with a segmented Bloom filter. In Proc. of the 19th International Conference on Architecture of Computing Systems, pages 283-297, March 2006.
12. L. Hammond, V. Wong, M. Chen, B. D. Carlstrom, J. D. Davis, B. Hertzberg, M. K. Prabhu, H. Wijaya, C. Kozyrakis, and K. Olukotun. Transactional memory coherence and consistency. In Proc. of the 31st Annual International Symposium on Computer Architecture, June 2004.
13. M. Herlihy and J. E. B. Moss. Transactional memory: Architectural support for lock-free data structures. In Proceedings of the Twentieth Annual International Symposium on Computer Architecture, pages 289-300, May 1993.
14. P. Kongetira, K. Aingaran, and K. Olukotun. Niagara: A 32-way multithreaded SPARC processor. IEEE Micro, 25(2):21-29, 2005.
15. J. R. Larus and R. Rajwar. Transactional Memory. Morgan & Claypool Publishers, 2006.
16. M. M. Martin, D. J. Sorin, B. M. Beckmann, M. R. Marty, M. Xu, A. R. Alameldeen, K. E. Moore, M. D. Hill, and D. A. Wood. Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset. Computer Architecture News, pages 92-99, Sept. 2005.
17. C. C. Minh, M. Trautmann, J. Chung, A. McDonald, N. Bronson, J. Casper, C. Kozyrakis, and K. Olukotun. An effective hybrid transactional memory system with strong isolation guarantees. In Proc. of the 34th Annual International Symposium on Computer Architecture, June 2007.
18. K. E. Moore, J. Bobba, M. J. Moravan, M. D. Hill, and D. A. Wood. LogTM: Log-based transactional memory. In Proc. of the 12th International Symposium on High-Performance Computer Architecture, pages 254-265, Feb 2006.
19. A. Pagh, R. Pagh, and S. S. Rao. An optimal Bloom filter replacement. In Proc. of the 16th Annual ACM-SIAM Symposium on Discrete Algorithms, pages 823-829, 2005.
20. R. Pagh and F. F. Rodler. Cuckoo hashing. In Proc. of the 9th Annual European Symposium on Algorithms, pages 121-133, 2001.
21. R. Rajwar, M. Herlihy, and K. Lai. Virtualizing transactional memory. In Proc. of the 32nd Annual International Symposium on Computer Architecture, pages 494-505, 2005.
22. M. V. Ramakrishna. Practical performance of Bloom filters and parallel free-text searching. Commun. ACM, 32(10):1237-1239, 1989.
23. M. V. Ramakrishna, E. Fu, and E. Bahcekapili. Efficient hardware hashing functions for high performance computers. IEEE Trans. Comput., 46(12):1378-1381, 1997.
24. E. Safi, A. Moshovos, and A. Veneris. L-CBF: a low-power, fast counting Bloom filter architecture. In Proc. of the 2006 International Symposium on Low Power Electronics and Design, pages 250-255, 2006.
25. D. Sanchez. Design and Implementation of Signatures for Transactional Memory Systems. Technical Report CS-TR-2007-1611, University of Wisconsin-Madison, Aug. 2007.
26. S. Sethumadhavan, R. Desikan, D. Burger, C. R. Moore, and S. W. Keckler. Scalable hardware memory disambiguation for high ILP processors. In Proc. of the 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003.
27. D. Tarjan, S. Thoziyoor, and N. P. Jouppi. CACTI 4.0. Technical Report HPL-2006-86, HP Labs, 2006.
28. H. Vandierendonck and K. D. Bosschere. XOR-based hash functions. IEEE Trans. Comput., 54(7):800-812, 2005.
29. J.-M. Wang, S.-C. Fang, and W.-S. Feng. New efficient designs for XOR and XNOR functions on the transistor level. IEEE Journal of Solid-State Circuits, 29(7):780-786, July 1994.
30. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The SPLASH-2 programs: Characterization and methodological considerations. In Proc. of the 22nd Annual International Symposium on Computer Architecture, pages 24-36, June 1995.
31. L. Yen, J. Bobba, M. R. Marty, K. E. Moore, H. Volos, M. D. Hill, M. M. Swift, and D. A. Wood. LogTM-SE: Decoupling hardware transactional memory from caches. In Proc. of the 13th International Symposium on High-Performance Computer Architecture, pages 261-272, Feb 2007.
32. A. Zeichick. One, two, three, four: A sneak peek inside AMD's forthcoming quad-core processors. Technical report, AMD, Jan. 2007.
33. C. Zilles and R. Rajwar. Transactional memory and the birthday paradox. In Proc. of the 19th Annual ACM Symposium on Parallel Algorithms and Architectures, pages 303-304, 2007.