A self-controllable-voltage-level (SVL) circuit for low- power, high-speed CMOS circuits

European Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 411-414

  Enomoto, Tadayoshi ^a   Oka, Yoshinori ^a   Shikano, Hiroaki ^a   Harada, Tomochika ^a  

^a CHUO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP AREAS; CMOS CIRCUITS; CMOS LOGIC CIRCUITS; DC VOLTAGE; MEMORY CELL ARRAYS; OUTPUT SIGNAL; STAND-BY LEAKAGE; STANDBY MODE;

ADDERS; CMOS INTEGRATED CIRCUITS; STATIC RANDOM ACCESS STORAGE;

LOW POWER ELECTRONICS;

EID: 0037774012     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. S. Mutoh, S. Shigematsu, Y. Matsuya, H. Fukuda, and J. Yamada, "A 1V multi-threshold voltage CMOS DSP with an efficient power management technique for mobile phone application," Digest of Technical Papers, IEEE International Solid-State Circuits Conference (ISSCC'96), FA 10.4, pp. 168-169, 438, Feb. 1996.
2. T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. Yoshioka, K. Suzuki, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakumu, and T. Sakurai, "A 0.9-V, 150-MHz, 10-mW, 4mm2 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme," IEEE Jour. of Solid-State Circuits, vol. 31, no. 11, pp. 1770-1779, Nov. 1996.
3. Veendrick, H. J. M., Deep-submicron CMOS ICs, Kuluwer academic publishers, Dordrecht, Netherlands, pp. 73-75, 1998.