High resolution body bias techniques for reducing the impacts of leakage current and parasitic bipolar

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2005, Pages 203-208

  Sumita, Masaya ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

Band to band tunneling; Body bias generator; CMOS scaling; Dead lock; Leakage components; Leakage current; Process compensation; Process variation; Substrate bias

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRON TUNNELING; NETWORKS (CIRCUITS); POWER ELECTRONICS; THRESHOLD VOLTAGE;

BAND-TO-BAND TUNNELING; CMOS SCALING; DEAD LOCK; LEAKAGE COMPONENTS; PROCESS COMPENSATION; PROCESS VARIATION; SUBSTRATE BIAS;

LEAKAGE CURRENTS;

EID: 28444494090     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/lpe.2005.195515     Document Type: Conference Paper

References (8)

1. S. Narendra et al., "1.1V 1GHz Communication Router with On-Chip Body Bias in 150nm CMOS," ISSCC, pp. 270-271, Feb. 2002.
2. T.Kobayashi, and T.Sakurai, "Self-Adjusting Threshold Voltage Scheme (SATS) For Low-Voltage High Speed Active mode," Proceedings of IEEE 1992 CICC, pp. 271-274 1992.
3. M.Sumita, S.Sakiyama, M.Kinoshita, Y.Araki, Y.Ikeda, and K.Fukuoka, "Mixed Body Bias Techniques with Fixed Vt and Ids Generation Circuits," ISSCC Digest of Technical Papers, pp. 158-159, Feb. 2004
4. C.Neau and K.Roy, "Optimal Body Bias Selection for Leakage Improvement and Process Compensation Over Different Technology Generations," Proceedings of 2003 ISLPED, pp. 116-121, Aug. 2003.
5. J.Tschanz, J.Kao, S.Narendra, R. Nair, D.Antoniadis, A.Chandrakasan, and V.De, "Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variation on Microprocessor Frequency and Leakage," ISSCC Digest of Technical Papers, pp. 412-413, Feb. 2002.
6. M.Miyazaki et al., "A 100-MIPS/W Microprocessor using Speed-Adaptive Threshold-Voltage CMOS with Forward Bias," ISSCC, pp. 420-421, Feb. 2000.
7. C.Kim et al., "An On-Die CMOS Leakage Current Sensor for Measuring Process Variation in Sub-90nm Generations," Symposium on VLSI Circuits Digest of Technical Papers, pp.250-251, June, 2004.
8. H.Ananthan, C.Kim, and K.Roy, "Larger-than-Vdd Forward Body Bias in Sub-0.5V Nanoscale CMOS," Proceedings of 2004 ISLPED, pp. 8-13, Aug. 2004.