A novel sub-1 v high speed circuit design technique in partially depleted SOI-CMOS technology with ultra low-leakage power

European Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 267-270

  Das, Koushik K ^a   Brown, Richard B ^a  

^a Department of Ecology and Evolutionary Biology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOST CIRCUITS; DYNAMIC LOGIC CIRCUITS; HIGH SPEED CIRCUIT; LEAKAGE POWER; PARTIALLY DEPLETED; PROCESS PARAMETERS; SUPPLY VOLTAGES; THREE ORDERS OF MAGNITUDE;

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE;

LEAKAGE CURRENTS;

EID: 46749122379     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Shin'ichiro Mutoh, et al., "1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS," IEEE Journal of Solid-State Circuits, August 1995, pp. 847-854.
2. Tadahiro Kuroda, et al., "A 0.9V, 150-MHz, 10-mW, 4mm2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme," IEEE Journal of Solid-State Circuits, November 1996, pp. 1770-1779.
3. Hiroshi Kawaguchi, et al., "A Super Cut-off CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage with Picoampere Stand-By Current," IEEE Journal of Solid-State Circuits, Vol. 35, No. 10, Oct. 2000, pp. 1498-1501.
4. Mario R. Casu and Gianluca Piccinini, "Synthesis of Low-Leakage PD-SOI Circuits with Body-Biasing," ISLPED 2001, pp. 287-290.
5. James T. Kao and Anantha Chandrakasan, "Dual Threshold Voltage Techniques for Low-Power Digital Circuits," IEEE Journal of Solid-State Circuits, Vol. 35, No. 7, July 2000, pp. 1009-1018.
6. Koji Fujii, Takakuni Douseki and Yuichi Kado, "A Sub-1V Dual-Threshold Domino Circuit Using Product-of-Sum Logic," ISLPED 2001, pp. 259-262.