A process-independent, 800-MB/s, DRAM byte-wide interface featuring command interleaving and concurrent memory operation

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 11, 1998, Pages 1741-1751

  Griffin, Matthew M ^a,b,c,d,e,f   Zerbe, Jared ^a,b,g,h,i   Tsang, Grace ^b,j,k,l,m   Ching, Michael ^a,b,d,e,n   Portmann, Clemenz L ^a,b,g,h,o,p  

^a IEEE   (United States)

^b RAMBUS INC   (United States)

^c UNIVERSITY OF KANSAS   (United States)

^d UNIVERSITY OF CALIFORNIA   (United States)

^e INTEL CORPORATION   (United States)

^f Inova Microelectronics   (United States)

^g STANFORD UNIVERSITY   (United States)

^h PHILIPS RESEARCH LABORATORIES   (Germany)

ⁱ MIPS Computer Systems

^j MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^k CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

^l TEKTRONIX INC   (United States)

^m WESTERN DIGITAL CORPORATION   (United States)

ⁿ NXP SEMICONDUCTORS   (Netherlands)

^o UNIVERSITY OF WASHINGTON   (United States)

^p UNIVERSITY OF HAWAII   (United States)

more..

Author keywords

CAD; Data communication; Delay locked loop; DRAM; Phase locked loop

Indexed keywords

COMPUTER AIDED DESIGN; DATA COMMUNICATION SYSTEMS; INTERFACES (COMPUTER); MICROPROCESSOR CHIPS; PHASE LOCKED LOOPS;

DELAY LOCKED LOOPS (DLL);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0032203877     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.726569     Document Type: Article

References (9)

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