Reducing the scheduling critical cycle using wakeup prediction

IEEE High-Performance Computer Architecture Symposium Proceedings

Volumn 10, Issue , 2004, Pages 222-231

  Ehrhart, Todd E ^a   Patel, Sanjay J ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FEEDBACK PARAMETERS; PROGRAM EXECUTION; STATIC INSTRUCTIONS; WAKEUP PREDICTION;

BENCHMARKING; COMPUTER SIMULATION; FEEDBACK; FORMAL LOGIC; GLOBAL OPTIMIZATION; PARALLEL PROCESSING SYSTEMS; PROBABILITY; PROGRAM PROCESSORS; SCHEDULING;

MICROPROCESSOR CHIPS;

EID: 2342508306     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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3. Ramon Canal and Antonio González, "A Low-Complexity Issue Logic", ICS 2000, pp. 327-335.
4. Dan Ernst, Andrew Hamel, and Todd Austin, "Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay", ISCA-30, 2003.
5. Pierre Michaud and André Seznec, "Data-flow Prescheduling for Large Instruction Windows in Out-of-order Processors", HPCA-6, 2001.
6. J. Stark, M. D. Brown, and Y. N. Patt, "On Pipelining Dynamic Instruction Scheduling Logic", MICRO-33, 2000.
7. Mary D. Brown, Jared Stark, and Yale N. Patt, "Select-Free Instruction Scheduling Logic", MICRO-34, 2001.
8. S. A. Mahlke, et al., "Sentinel Scheduling for VLIW and Superscalar Procesors", ACM Transactions on Computer Systems, 11(4):376-408, 1993.
9. B. Slechta, et al., "Dynamic Optimization of Micro-Operations", HPCA-9, 2003.