Instruction replication: Reducing delays due to inter-PE communication latency

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn 2003-January, Issue , 2003, Pages 46-55

  Aggarwal, Aneesh ^a   Franklin, Manoj ^a  

^a UNIVERSITY OF MARYLAND   (United States)

Author keywords

Clustered processors; Instruction Distribution; Instruction Replication; Instructions per Cycle; Inter PE communication; Load Imbalance

Indexed keywords

PARALLEL PROCESSING SYSTEMS;

CLUSTERED PROCESSORS; INSTRUCTION DISTRIBUTIONS; INSTRUCTION REPLICATION; INSTRUCTIONS PER CYCLES; LOAD IMBALANCE;

PARALLEL ARCHITECTURES;

EID: 33746287193     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2003.1238001     Document Type: Conference Paper

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