메뉴 건너뛰기




Volumn , Issue , 2006, Pages 563-567

Combinatorial algorithms for fast clock mesh optimization

Author keywords

[No Author keywords available]

Indexed keywords

CANDIDATE LOCATIONS; CLOCK SKEWS; COMBINATORIAL ALGORITHMS; COMPUTER-AIDED DESIGN; DELAY PENALTY; EXPERIMENTAL RESULTS; INTERNATIONAL CONFERENCES; MESH ARCHITECTURE; MESH OPTIMIZATION; POWER DISSIPATIONS; POWER SAVINGS; PROCESS VARIATIONS; SURVIVABLE NETWORKS; WIRE LENGTHS;

EID: 46149087308     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2006.320175     Document Type: Conference Paper
Times cited : (35)

References (24)
  • 1
    • 0033699258 scopus 로고    scopus 로고
    • Impact of interconnect variations on the clock skew of a gigahertz microprocessor
    • Y. Liu, S. R. Nassif, L. T. Pileggi, and A. J. Strojwas. Impact of interconnect variations on the clock skew of a gigahertz microprocessor. DAC, pages 168-171, 2000.
    • (2000) DAC , pp. 168-171
    • Liu, Y.1    Nassif, S.R.2    Pileggi, L.T.3    Strojwas, A.J.4
  • 2
    • 0025464163 scopus 로고
    • Clock skew optimization
    • J. P. Fishburn. Clock skew optimization. IEEE Transactions on Computers, vol. 39, no. 7. pages 945-950, 1990.
    • (1990) IEEE Transactions on Computers , vol.39 , Issue.7 , pp. 945-950
    • Fishburn, J.P.1
  • 3
    • 0026946698 scopus 로고    scopus 로고
    • T.-H. Chao, Y.-C. Hsu, J.-M. Ho, K. D. Boese, and A. B. Kahng. Zero skew clock routing with minimum wirelength. IEEE Transactions on Circuits and Systems - Analog and Digital Signal Processing, 39(11):799-814, November 1992.
    • T.-H. Chao, Y.-C. Hsu, J.-M. Ho, K. D. Boese, and A. B. Kahng. Zero skew clock routing with minimum wirelength. IEEE Transactions on Circuits and Systems - Analog and Digital Signal Processing, 39(11):799-814, November 1992.
  • 5
    • 0035334849 scopus 로고    scopus 로고
    • A clock distribution network for microprocessors
    • May
    • P. J. Restle et al. A clock distribution network for microprocessors. IEEE Journal of Solid-State Circuits, 36(5):792-799, May 2001.
    • (2001) IEEE Journal of Solid-State Circuits , vol.36 , Issue.5 , pp. 792-799
    • Restle, P.J.1
  • 6
    • 33751427891 scopus 로고    scopus 로고
    • Scalable sub-10 ps skew global clock distribution for a 90nm multi-GHz IA microprocessor
    • N. Bindal, T. Kelly, N. Velastegui, and K. L. Wong. Scalable sub-10 ps skew global clock distribution for a 90nm multi-GHz IA microprocessor. In Proceedings of the ISSCC, pages 346-355, 2003.
    • (2003) Proceedings of the ISSCC , pp. 346-355
    • Bindal, N.1    Kelly, T.2    Velastegui, N.3    Wong, K.L.4
  • 7
    • 4444311842 scopus 로고    scopus 로고
    • Reducing clock skew variability via cross links
    • A. Rajaram. J. Hu. and R. Mahapatra. Reducing clock skew variability via cross links. In DAC, pages 18-23, 2004.
    • (2004) DAC , pp. 18-23
    • Rajaram, A.1    Hu, J.2    Mahapatra, R.3
  • 8
    • 0002645865 scopus 로고    scopus 로고
    • 609 MHz G5 S/399 microprocessor.
    • G. Northrop et. al. 609 MHz G5 S/399 microprocessor. In ISSCC, pages 88-89, 1999.
    • (1999) ISSCC , pp. 88-89
    • Northrop, G.1    et., al.2
  • 9
    • 0036113803 scopus 로고    scopus 로고
    • The clock distribution of the Power 4 microprocessor
    • P. J. Restle et. al. The clock distribution of the Power 4 microprocessor. In , ISSCC, pages 144-145, 2002.
    • (2002) ISSCC , pp. 144-145
    • Restle, P.J.1    et., al.2
  • 10
    • 0034429687 scopus 로고    scopus 로고
    • Implementation of a 3rd-generation SPARC V9 64 b microprocessor
    • R. Heald. Implementation of a 3rd-generation SPARC V9 64 b microprocessor. In ISSCC, pages 412-413, 2000.
    • (2000) ISSCC , pp. 412-413
    • Heald, R.1
  • 11
    • 0035215162 scopus 로고    scopus 로고
    • Hybrid structured clock network construction
    • H. Su and S. Sapatnekar. Hybrid structured clock network construction. In ICCAD, pages, 333-336, 2001.
    • (2001) ICCAD , pp. 333-336
    • Su, H.1    Sapatnekar, S.2
  • 14
    • 23244465489 scopus 로고    scopus 로고
    • Design of Survivable Networks: A survey
    • April
    • H. Kerivin and A. R. Mahjoub. Design of Survivable Networks: A survey. In Networks, pages 1-21, April 2005.
    • (2005) Networks , pp. 1-21
    • Kerivin, H.1    Mahjoub, A.R.2
  • 15
    • 0034239439 scopus 로고    scopus 로고
    • Constrained length connectivity and survivable networks
    • August
    • W Ben-Ameur. Constrained length connectivity and survivable networks. In Networks, pages 17-23, August 2000.
    • (2000) Networks , pp. 17-23
    • Ben-Ameur, W.1
  • 16
    • 0028756124 scopus 로고    scopus 로고
    • J. Qian and S. Pullela and L. Pillage. Modeling the 'Effective Capacitance' of RC Interconnect. In IEEE Trans. Computer-Aided Design, pages 1526-1535, December 1994.
    • J. Qian and S. Pullela and L. Pillage. Modeling the 'Effective Capacitance' of RC Interconnect. In IEEE Trans. Computer-Aided Design, pages 1526-1535, December 1994.
  • 17
    • 0028576150 scopus 로고    scopus 로고
    • F. Dartu and N. Menezes and J. Qian and L. Pillage. A gate-delay model for high speed CMOS circuits. In DAC, pages 576-580, June 1994.
    • F. Dartu and N. Menezes and J. Qian and L. Pillage. A gate-delay model for high speed CMOS circuits. In DAC, pages 576-580, June 1994.
  • 18
    • 0031333601 scopus 로고    scopus 로고
    • CMOS gate delay models for general RLC loading
    • October
    • R. Arunachalam, F. Dartu and L. Pileggi. CMOS gate delay models for general RLC loading. In ICCAD, pages 224-229, October 1997.
    • (1997) ICCAD , pp. 224-229
    • Arunachalam, R.1    Dartu, F.2    Pileggi, L.3
  • 19
    • 0041633843 scopus 로고    scopus 로고
    • Blade and Razor: Cell and Interconnect Delay Analysis Using Current-Based Models
    • June
    • J. Croix and D. Wong. Blade and Razor: Cell and Interconnect Delay Analysis Using Current-Based Models. In DAC, pages 386-389, June 2006.
    • (2006) DAC , pp. 386-389
    • Croix, J.1    Wong, D.2
  • 20
    • 33748535745 scopus 로고    scopus 로고
    • A waveform independent gate model for accurate timing analysis
    • October
    • P. Li and E. Acar. A waveform independent gate model for accurate timing analysis. In ICCD, pages 363-365, October 2005.
    • (2005) ICCD , pp. 363-365
    • Li, P.1    Acar, E.2
  • 21
    • 16244373361 scopus 로고    scopus 로고
    • A robust cell-level crosstalk delay change analysis
    • November
    • I. Keller, K. Tseng and N. Verghese. A robust cell-level crosstalk delay change analysis. In ICCAD, pages 147-154, November 2004.
    • (2004) ICCAD , pp. 147-154
    • Keller, I.1    Tseng, K.2    Verghese, N.3
  • 22
    • 46149090526 scopus 로고    scopus 로고
    • http://www.eas.asu.edu/ptm/.
  • 23
    • 33749346335 scopus 로고    scopus 로고
    • Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization
    • February
    • A. B. Kahng and B. Liu. Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization. IEEE Camp. Soc. Annual Symp. On VLSI, pages 183-188, February, 2003.
    • (2003) IEEE Camp. Soc. Annual Symp. On VLSI , pp. 183-188
    • Kahng, A.B.1    Liu, B.2
  • 24
    • 0346778721 scopus 로고    scopus 로고
    • Statistical timing analysis considering spatial correlations using a single PERT-like traversal
    • H. Chang and S. S. Sapatnekar. Statistical timing analysis considering spatial correlations using a single PERT-like traversal. In ICCAD , pages 621-625, 2003.
    • (2003) ICCAD , pp. 621-625
    • Chang, H.1    Sapatnekar, S.S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.