Q-Tree: a new iterative improvement approach for buffered interconnect optimization

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

Volumn 2003-January, Issue , 2003, Pages 183-188

  Kahng, Andrew B ^a   Liu, Bao ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Capacitance; Delay; Iterative algorithms; Iterative methods; Logic design; Routing; Steiner trees; Timing; Topology; Very large scale integration

Indexed keywords

ALGORITHMS; CAPACITANCE; ITERATIVE METHODS; LOGIC DESIGN; OPTIMIZATION; TOPOLOGY; TREES (MATHEMATICS); VLSI CIRCUITS;

DELAY; ITERATIVE ALGORITHM; ROUTING; STEINER TREES; TIMING;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 33749346335     PISSN: 21593469     EISSN: 21593477     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2003.1183444     Document Type: Conference Paper

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