Despite engineering and cost challenges, 32nm node IC manufacturing within reach

Solid State Technology

Volumn 51, Issue 5, 2008, Pages 26-33

  Arghavani, Reza ^a   M'saad, Hichem ^a  

^a APPLIED MATERIALS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

TECHNOLOGY;

(100) SILICON; 45 NM TECHNOLOGY; BIAXIAL STRESSES; DISRUPTIVE TECHNOLOGIES; DOUBLE GATE (DG); HIGH VOLUME MANUFACTURE (HVM); IC MANUFACTURING; INTEGRATION METHODS; MANUFACTURABILITY; NEW MATERIALS; NODE TECHNOLOGY; PLANAR TRANSISTORS; TRANSITION (JEL CLASSIFICATIONS:E52 ,E41 ,E31); UNIAXIAL STRESSES;

NANOTECHNOLOGY;

EID: 45849107661     PISSN: 0038111X     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article

References (22)

1. H. S. Yang et al., "Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing," in IEDM Tech. Dig., Dec. 2004, pp. 1075-1078.
2. R. Arghavani et al., "Strain engineering push to the 32nm logic technology node," in Semiconductor Fabtech, 32nd Edition, 2007.
3. K. Mistry et al., "A 45nm logic technology with high-k+metal gate transistor, strained silicon, 9Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging," in IEDM Tech. Dig., Dec. 2007, pp. 247-250.
4. J. W. Sleight et al., "Challenges and opportunities for high performance 32nm CMOS technology," in IEDM Tech. Dig., Dec. 2006, pp. 697-700.
5. R. Arghavani et al., "External resistance: a paradigm shift in approaching strain engineering," in Semiconductor Fabtech, 35th Edition, 2007.
6. L. Washington et al., "pMOSFET with 200% mobility enhancement induced by multiple stressors,"IEEE Electron Device Lett., vol. 26, no. 6, June 2006, pp. 511-513.
7. M. Chudzik et al., "High-performance high-k/metal gates for 45nm CMOS and beyond with gate-first processing," in VLSI Tech. Dig., 2007, pp. 194-195.
8. R. Chau et al., "Advanced CMOS transistors in the nanotechnology era for high-performance, low-power logic applications," in ICSICT Tech. Dig., 2004, pp. 26-30.
9. E. R Gusev, V. Narayanan, and M. M. Frank, "Advanced high-k dielectric stacks with polySi and metal gates: Recent progress and current challenges," in IBM J. Res. & Dev., vol. 90, no. 4/5, Jul./Sept. 2006, pp. 387.
10. V. Narayanan et al., "Band-edge high-performance high-k/metal gate n-MOSFETs using cap layers containing group IIA and IIIB elements with gate-first processing for 45nm and beyond," in VLSI Tech. Dig., 2006, pp. 178-179.
11. H. N. Alshareef et al., "Metal gate work function engineering using AlNx interfacial layers," Appl. Phys. Lett., vol. 88, 2006, pp. 112-114.
12. M. V. Fischetti, D. A. Neumayer, and E. A. Cartier, "Effective electron mobility in Si inversion layers in metal-oxide-semiconductor systems with a high-k insulator: The role of remote phonon scattering." J. Appl. Phys., vol. 90, no. 9, 2001, pp. 4587-4608.
13. S. Sankaran et al., "A 45nm CMOS node Cu/low-k/ultra low-k PECVD SiCOH (k=2.4) BEOL technology," in IEDM Tech. Dig., 2006.
14. M. T. Bohr, "Interconnect scaling - The real limiter to high performance ULSI," in IEDM Tech. Dig, 1995, pp. 241-244.
15. R. Cheung and D. Hoffman, "Physics and process drive etch performance at 45nm," in Solid State Technology, March 2005, pp. 27.
16. R. Fox et al., "High Performance k=2.5 ULK Backend Solution Using an Improved TFHM Architecture, Extendible to the 45nm Technology Node," in IEDM Tech. Dig, 2005.
17. J. Van Olmen et al., "Cu resistivity scaling limits for 20nm copper damascene lines," in IITC Tech. Dig, 2007, pp. 49-51.
18. D. Edelstein et al., "A High Performance Liner for Copper Damascene Interconnects," in IITC Tech. Dig, 2001, pp. 9-11.
19. J. Van Olmen et al., "Integration of 50nm half pitch single damascene copper trenches in BDIIx by means of double patterning 193nm immersion lithography on metal hardmask," in AMC Tech. Dig., 2007, pp. 5.
20. L. Karuppiah et al., "Overview of CMP Process Control Strategies," in CMP-MIC Tech. Dig., February 2006, pp. 45-54.
21. S. Narasimha et al., "High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography," in IEDM Tech. Dig. 2006, pp. 1-4.
22. 2 6T-SRAM Cell by Immersion Lithography," in VLSI Tech. Dig, 2005, pp. 16-17.