Novel 20nm hybrid SOI/bulk CMOS Technology with 0.183μm2 6T-SRAM cell by immersion lithography

Digest of Technical Papers - Symposium on VLSI Technology

Volumn 2005, Issue , 2005, Pages 16-17

  Chen, Hou Yu ^a   Chang, Chang Yun ^a   Huang, Chien Chao ^a   Chung, Tang Xuan ^a   Liu, Sheng Da ^a   Hwang, Jiunn Ren ^a   Liu, Yi Hsuan ^a   Chou, Yu Jun ^a   Wu, Hong Jang ^a   Shu, King Chang ^a   Huang, Chung Kan ^a   You, Jan Wen ^a   Shin, Jaw Jung ^a   Chen, Chun Kuang ^a   Lin, Chia Hui ^a   Hsu, Ju Wang ^a   Perng, Bao Chin ^a   Tsai, Pang Yen ^a   Chen, Chi Chun ^a   Shieh, Jyu Horng ^a   Tao, Han Jan ^a   Chen, Shih Chang ^a   Gau, Tsai Sheng ^a   Yang, Fu Liang ^a   more..

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CONTROL SYSTEMS; DELAY CIRCUITS; DIELECTRIC DEVICES; LEAKAGE CURRENTS; LITHOGRAPHY; SILICON ON INSULATOR TECHNOLOGY;

INTRINSIC GATE DELAY; SION GATE DIELECTRIC; VIRTUAL BACK-GATE CONTROL;

CMOS INTEGRATED CIRCUITS;

EID: 33745151094     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/.2005.1469194     Document Type: Conference Paper

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