Influences of nonuniformity in metal concentration in gate dielectric silicate on CMIS inverters' propagation delay time

Solid-State Electronics

Volumn 48, Issue 12, 2004, Pages 2191-2198

  Ono, Mizuki ^a   Ino, Tsunehiro ^a   Koyama, Masato ^a   Takashima, Akira ^a   Nishiyama, Akira ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC INVERTERS; GATES (TRANSISTOR); PERMITTIVITY; PHASE SEPARATION; POLARIZATION; SEMICONDUCTING FILMS;

GATE DIELECTRICS; METAL CONCENTRATION; THREE DIMENSIONAL DEVICE SIMULATION;

MISFET DEVICES;

EID: 4544367261     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2004.05.049     Document Type: Article

References (14)

1. Ono M., Saito M., Yoshitomi T., Fiegna C., Ohguro T., Iwai H. A 40 nm gate length nMOSFET. IEEE Trans. Electron. Dev. ED-42(10):1995;1822-1830.
2. Tsuji K, Takeuchi K, Mogami T. High performance 50-nm physical gate length pMOSFETs by using low temperature activation by re-crystallization scheme. Tech Dig of 1999 Symposium on VLSI Technology. p. 9-10.
3. Goto K, Sambonsugi Y, Sugii T. Co Salicide compatible 2-step activation annealing process for deca-nano scaled MOSFETs. Tech Dig of 1999 Symposium on VLSI Technology. p. 49-50.
4. Caillat C, Deleonibus S, Guegan G, Tedesco S, Dal'zotto B, Heitzmann M, et al. 65 nm physical gate length NMOSFETs with heavy ion implanted pockets and highly reliable 2 nm-thick gate oxide for 1.5 V operation. Tech Dig of 1999 Symposium on VLSI Technology. p. 89-90.
5. Chau R., Kavalieros J., Roberds B., Schenker R., Lionberger D., Barlage D., et al. 30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays. IEDM Tech. Dig. 2000;45-48.
6. Wakabayashi H., Ueki M., Narihiro M., Fukai T., Ikezawa N., Matsuda T., et al. 45-nm gate length CMOS technology and beyond using steep halo. IEDM Tech. Dig. 2000;49-52.
7. The International Technology Roadmap for Semiconductors: 2001 Update. Available from: http://public.itrs.net/.
8. Wilk G.D., Wallace R.M., Anthony J.M. High-. κ gate dielectrics: current status and materials properties considerations J. Appl. Phys. 89(10):2001;5243-5275.
9. Kingon A.I., Maria J.P., Streiffer S.K. Alternative dielectrics to silicon dioxide for memory and logic devices. Nature. 406(6799):2000;1032-1038.
10. 2-rich noncrystalline Zr and Hf silicate alloys. Appl. Phys. Lett. 77(18):2000;2912-2914.
11. Chindalore G., Shih W.K., Jallepalli S., Hareland S.A., Tasch A.F., Maziar C.M. An experimental study of the effect of quantization on the effective electrical oxide thickness in MOS electron and hole accumulation layers in heavily doped Si. IEEE Trans. Electron Dev. ED-47(3):2000;643-646.
12. Takagi S., Toriumi A., Iwase M., Tango H. On the universality of inversion layer mobility in Si MOSFET's: Part I - effects of substrate impurity concentration. IEEE Trans. Electron Dev. ED-41(12):1994;2357-2362.
13. Yamaguchi T., Satake H., Fukushima N. Degradation of current drivability by the increase of Zr concentrations in Zr-silicate MISFET. IEDM Tech. Dig. 2001;663-666.
14. 3 gate dielectric. Tech Dig of 2002 Symposium on VLSI Technology. p. 188-9.