High performance 50-nm physical gate length pMOSFETs by using low temperature activation by re-crystallization scheme

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1999, Pages 9-10

  Tsuji, K ^a   Takeuchi, K ^a   Mogami, T ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMORPHOUS MATERIALS; CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); LOW TEMPERATURE OPERATIONS; SUBSTRATES;

AMORPHOUS SUBSTRATE LAYER; DRAIN IMPURITY; LOW TEMPERATURE ACTIVATION;

MOSFET DEVICES;

EID: 0033280895     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)