메뉴 건너뛰기




Volumn , Issue CIRCUITS SYMP., 2004, Pages 334-337

Microprocessor power optimization through multi-performance device insertion

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT DELAY; DYNAMIC POWER; PERFORMANCE GAIN; STATIC-TIMING ANALYSIS;

EID: 4544284893     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (7)

References (10)
  • 1
    • 0030387081 scopus 로고    scopus 로고
    • 0.18um dual Vt MOSFET process and energy-delay measurement
    • Dec.
    • Z. Chen, et al., "0.18um Dual Vt MOSFET Process and Energy-Delay Measurement," in IEDM, Dec. 1996, pp. 851-854.
    • (1996) IEDM , pp. 851-854
    • Chen, Z.1
  • 2
    • 0031642549 scopus 로고    scopus 로고
    • A highly manufacturable 0.25μm multiple-Vt dual gate oxide CMOS process for logic/embedded IC foundry technology
    • June
    • M. H. Chang, et al., "A Highly Manufacturable 0.25μm Multiple-Vt Dual Gate Oxide CMOS Process for Logic/Embedded IC Foundry Technology," in Symp. VLSI Tech., June 1998, pp. 150-151.
    • (1998) Symp. VLSI Tech. , pp. 150-151
    • Chang, M.H.1
  • 3
    • 0034430274 scopus 로고    scopus 로고
    • A 450MHz 64b RISC processor using multiple threshold voltage CMOS
    • Feb.
    • T. Yamashita, et al., "A 450MHz 64b RISC Processor using Multiple Threshold Voltage CMOS," in ISSCC, Feb. 2000, pp. 414-415.
    • (2000) ISSCC , pp. 414-415
    • Yamashita, T.1
  • 4
    • 0033680440 scopus 로고    scopus 로고
    • High-performance low-power CMOS circuits using multiple channel length and multiple oxide thickness
    • Sept.
    • N. Sirisantana, L. Wei, and K. Roy, "High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness," in ICCAD, Sept. 2000, pp. 227-232.
    • (2000) ICCAD , pp. 227-232
    • Sirisantana, N.1    Wei, L.2    Roy, K.3
  • 5
    • 0034453378 scopus 로고    scopus 로고
    • CMOS device optimization for system-on-a-chip applications
    • Dec.
    • K. Imai, et al., "CMOS device optimization for system-on-a-chip applications," in IEDM, Dec. 2000, pp. 455-458.
    • (2000) IEDM , pp. 455-458
    • Imai, K.1
  • 6
    • 0034452603 scopus 로고    scopus 로고
    • A 130nm generation logic technology featuring 70nm transistors, dual Vt transistors and 6 layers of Cu interconnects
    • Dec.
    • S. Tyagi, et al., "A 130nm Generation Logic Technology Featuring 70nm Transistors, Dual Vt Transistors and 6 layers of Cu Interconnects," in IEDM, Dec. 2000, pp. 567-570.
    • (2000) IEDM , pp. 567-570
    • Tyagi, S.1
  • 7
    • 0036931972 scopus 로고    scopus 로고
    • A 90 nm logic technology featuring 50nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 um2 SRAM cell
    • Dec
    • S. Thompson, et al., "A 90 nm Logic Technology Featuring 50nm Strained Silicon Channel Transistors, 7 layers of Cu Interconnects, Low k ILD, and 1 um2 SRAM Cell," in IEDM, Dec 2002, pp. 61-64.
    • (2002) IEDM , pp. 61-64
    • Thompson, S.1
  • 8
    • 0037887527 scopus 로고    scopus 로고
    • Designing a 3GHz, 130nm, Intel ®Pentium® 4 Processor
    • June
    • D. Deleganes, et al., "Designing a 3GHz, 130nm, Intel ®Pentium® 4 Processor," in Symp. VLSI Circuits, June 2002, pp. 130-133.
    • (2002) Symp. VLSI Circuits , pp. 130-133
    • Deleganes, D.1
  • 9
    • 0036054545 scopus 로고    scopus 로고
    • Uncertainty-aware circuit optimization
    • June
    • X. Bai, et al., "Uncertainty-Aware Circuit Optimization," in DAC, June 2002, pp. 58-63.
    • (2002) DAC , pp. 58-63
    • Bai, X.1
  • 10
    • 0036474722 scopus 로고    scopus 로고
    • Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration
    • Feb.
    • K. A. Bowman, S. G. Duvall, and J. D. Meindl, "Impact of Die-to-Die and Within-Die Parameter Fluctuations on the Maximum Clock Frequency Distribution for Gigascale Integration," IEEE J. Solid-State Circuits, pp. 183-190, Feb. 2002.
    • (2002) IEEE J. Solid-state Circuits , pp. 183-190
    • Bowman, K.A.1    Duvall, S.G.2    Meindl, J.D.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.